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Log the time needed for compilation.
author
Matthijs Kooijman
<matthijs@stdin.nl>
Wed, 31 Mar 2010 11:01:47 +0000
(13:01 +0200)
committer
Matthijs Kooijman
<matthijs@stdin.nl>
Wed, 31 Mar 2010 11:01:47 +0000
(13:01 +0200)
cλash/CLasH/Translator.hs
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diff --git
a/cλash/CLasH/Translator.hs
b/cλash/CLasH/Translator.hs
index 04b7beb0900b14950dec9f5f0f00bc5454635666..79bd8d2e74ab9d7a97ace0d21849810f145add6d 100644
(file)
--- a/
cλash/CLasH/Translator.hs
+++ b/
cλash/CLasH/Translator.hs
@@
-12,6
+12,8
@@
import qualified Control.Monad.Trans.State as State
import Text.PrettyPrint.HughesPJ (render)
import Data.Accessor.Monad.Trans.State
import qualified Data.Map as Map
import Text.PrettyPrint.HughesPJ (render)
import Data.Accessor.Monad.Trans.State
import qualified Data.Map as Map
+import qualified Data.Time.Clock as Clock
+import Debug.Trace
-- GHC API
import qualified CoreSyn
-- GHC API
import qualified CoreSyn
@@
-71,6
+73,7
@@
makeVHDL ::
-> Finder
-> IO ()
makeVHDL libdir filenames finder = do
-> Finder
-> IO ()
makeVHDL libdir filenames finder = do
+ start <- Clock.getCurrentTime
-- Load the modules
(cores, env, specs) <- loadModules libdir filenames (Just finder)
-- Translate to VHDL
-- Load the modules
(cores, env, specs) <- loadModules libdir filenames (Just finder)
-- Translate to VHDL
@@
-80,7
+83,9
@@
makeVHDL libdir filenames finder = do
let dir = "./vhdl/" ++ (show top_entity) ++ "/"
prepareDir dir
mapM_ (writeVHDL dir) vhdl
let dir = "./vhdl/" ++ (show top_entity) ++ "/"
prepareDir dir
mapM_ (writeVHDL dir) vhdl
- return ()
+ end <- Clock.getCurrentTime
+ trace ("\nTotal compilation took " ++ show (Clock.diffUTCTime end start)) $
+ return ()
-- | Translate the specified entities in the given modules to VHDL.
moduleToVHDL ::
-- | Translate the specified entities in the given modules to VHDL.
moduleToVHDL ::