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Import the ieee library into the generated types package.
author
Matthijs Kooijman
<m.kooijman@student.utwente.nl>
Tue, 10 Mar 2009 16:55:29 +0000
(17:55 +0100)
committer
Matthijs Kooijman
<m.kooijman@student.utwente.nl>
Tue, 10 Mar 2009 16:55:29 +0000
(17:55 +0100)
VHDL.hs
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diff --git
a/VHDL.hs
b/VHDL.hs
index ae72368f4f9fd0b6eccbe9f20f7836ef0d4da733..4d8b6669d69503a7f8977eaac1996488648a9ccd 100644
(file)
--- a/
VHDL.hs
+++ b/
VHDL.hs
@@
-36,18
+36,21
@@
createDesignFiles ::
createDesignFiles flatfuncmap =
-- TODO: Output types
createDesignFiles flatfuncmap =
-- TODO: Output types
- (mkVHDLId "types", AST.DesignFile
[]
[type_package]) :
- map (Arrow.second $ AST.DesignFile context) units
+ (mkVHDLId "types", AST.DesignFile
ieee_context
[type_package]) :
+ map (Arrow.second $ AST.DesignFile
full_
context) units
where
init_session = VHDLSession Map.empty builtin_funcs
(units, final_session) =
State.runState (createLibraryUnits flatfuncmap) init_session
ty_decls = Map.elems (final_session ^. vsTypes)
where
init_session = VHDLSession Map.empty builtin_funcs
(units, final_session) =
State.runState (createLibraryUnits flatfuncmap) init_session
ty_decls = Map.elems (final_session ^. vsTypes)
- context = [
- AST.Library $ mkVHDLId "IEEE",
- AST.Use $ (AST.NSimple $ mkVHDLId "IEEE.std_logic_1164") AST.:.: AST.All,
- AST.Use $ (AST.NSimple $ mkVHDLId "work.types") AST.:.: AST.All]
+ ieee_context = [
+ AST.Library $ mkVHDLId "IEEE",
+ AST.Use $ (AST.NSimple $ mkVHDLId "IEEE.std_logic_1164") AST.:.: AST.All
+ ]
+ full_context =
+ (AST.Use $ (AST.NSimple $ mkVHDLId "work.types") AST.:.: AST.All)
+ : ieee_context
type_package = AST.LUPackageDec $ AST.PackageDec (mkVHDLId "types") (map (AST.PDITD . snd) ty_decls)
createLibraryUnits ::
type_package = AST.LUPackageDec $ AST.PackageDec (mkVHDLId "types") (map (AST.PDITD . snd) ty_decls)
createLibraryUnits ::