- genScheme = AST.ForGn nPar range
- -- Get the entity name and port names
- entity_id = ent_id entity
- argports = map fst (ent_args entity)
- resport = fst (ent_res entity)
- -- Assign the ports
- inport = mkAssocElemIndexed (argports!!0) (varToVHDLId arg) nPar
- outport = mkAssocElemIndexed resport (varToVHDLId res) nPar
- portassigns = [inport,outport]
- -- Generate the portmap
- mapLabel = "map" ++ (AST.fromVHDLId entity_id)
- compins = mkComponentInst mapLabel entity_id portassigns
- -- Return the generate functions
- genSm = AST.CSGSm $ AST.GenerateSm label genScheme [] [compins]
- in
- return $ [genSm]
+ genScheme = AST.ForGn n_id range
+
+ -- Create the content of the generate statement: Applying the mapped_f to
+ -- each of the elements in arg, storing to each element in res
+ resname = mkIndexedName (varToVHDLName res) n_expr
+ argexpr = vhdlNameToVHDLExpr $ mkIndexedName (varToVHDLName arg) n_expr
+ in do
+ app_concsms <- genApplication (Right resname) mapped_f [Right argexpr]
+ -- Return the generate statement
+ return [AST.CSGSm $ AST.GenerateSm label genScheme [] app_concsms]
+