+ genSm = AST.CSGSm $ AST.GenerateSm label genScheme [] [compins]
+
+genFoldlCall ::
+ Entity
+ -> [CoreSyn.CoreBndr]
+ -> VHDLSession AST.ConcSm
+genFoldlCall entity [startVal, inVec, resVal] = do
+ let (vec, _) = splitAppTy (Var.varType inVec)
+ let vecty = Type.mkAppTy vec (Var.varType startVal)
+ vecType <- vhdl_ty vecty
+ -- Setup the generate scheme
+ let len = (tfvec_len . Var.varType) inVec
+ let genlabel = mkVHDLExtId ("foldlVector" ++ (varToString inVec))
+ let blockLabel = mkVHDLExtId ("foldlVector" ++ (varToString startVal))
+ let nPar = AST.unsafeVHDLBasicId "n"
+ let range = AST.ToRange (AST.PrimLit "0") (AST.PrimLit $ show (len-1))
+ let genScheme = AST.ForGn nPar range
+ -- Make the intermediate vector
+ let tmpVec = AST.BDISD $ AST.SigDec (mkVHDLExtId "tmp") vecType Nothing
+ -- Return the generate functions
+ let genSm = AST.GenerateSm genlabel genScheme [] [ AST.CSGSm (genFirstCell entity [startVal, inVec, resVal])
+ , AST.CSGSm (genOtherCell entity [startVal, inVec, resVal])
+ , AST.CSGSm (genLastCell entity [startVal, inVec, resVal])
+ ]
+ return $ AST.CSBSm $ AST.BlockSm blockLabel [] (AST.PMapAspect []) [tmpVec] [AST.CSGSm genSm]
+ where
+ genFirstCell :: Entity -> [CoreSyn.CoreBndr] -> AST.GenerateSm
+ genFirstCell entity [startVal, inVec, resVal] = cellGn
+ where
+ cellLabel = mkVHDLExtId "firstcell"
+ cellGenScheme = AST.IfGn ((AST.PrimName $ AST.NSimple nPar) AST.:=: (AST.PrimLit "0"))
+ nPar = AST.unsafeVHDLBasicId "n"
+ -- Get the entity name and port names
+ entity_id = ent_id entity
+ argports = map (Monad.liftM fst) (ent_args entity)
+ resport = (Monad.liftM fst) (ent_res entity)
+ -- Assign the ports
+ inport1 = mkAssocElem (argports!!0) (varToString startVal)
+ inport2 = mkAssocElemIndexed (argports!!1) (varToString inVec) nPar
+ outport = mkAssocElemIndexed resport "tmp" nPar
+ clk_port = mkAssocElem (Just $ mkVHDLExtId "clk") "clk"
+ portassigns = Maybe.catMaybes [inport1,inport2,outport,clk_port]
+ -- Generate the portmap
+ mapLabel = "cell" ++ (AST.fromVHDLId entity_id)
+ compins = mkComponentInst mapLabel entity_id portassigns
+ -- Return the generate functions
+ cellGn = AST.GenerateSm cellLabel cellGenScheme [] [compins]
+ genOtherCell :: Entity -> [CoreSyn.CoreBndr] -> AST.GenerateSm
+ genOtherCell entity [startVal, inVec, resVal] = cellGn
+ where
+ len = (tfvec_len . Var.varType) inVec
+ cellLabel = mkVHDLExtId "othercell"
+ cellGenScheme = AST.IfGn $ AST.And ((AST.PrimName $ AST.NSimple nPar) AST.:>: (AST.PrimLit "0"))
+ ((AST.PrimName $ AST.NSimple nPar) AST.:<: (AST.PrimLit $ show (len-1)))
+ nPar = AST.unsafeVHDLBasicId "n"
+ -- Get the entity name and port names
+ entity_id = ent_id entity
+ argports = map (Monad.liftM fst) (ent_args entity)
+ resport = (Monad.liftM fst) (ent_res entity)
+ -- Assign the ports
+ inport1 = mkAssocElemIndexed (argports!!0) "tmp" (AST.unsafeVHDLBasicId "n-1")
+ inport2 = mkAssocElemIndexed (argports!!1) (varToString inVec) nPar
+ outport = mkAssocElemIndexed resport "tmp" nPar
+ clk_port = mkAssocElem (Just $ mkVHDLExtId "clk") "clk"
+ portassigns = Maybe.catMaybes [inport1,inport2,outport,clk_port]
+ -- Generate the portmap
+ mapLabel = "cell" ++ (AST.fromVHDLId entity_id)
+ compins = mkComponentInst mapLabel entity_id portassigns
+ -- Return the generate functions
+ cellGn = AST.GenerateSm cellLabel cellGenScheme [] [compins]
+ genLastCell :: Entity -> [CoreSyn.CoreBndr] -> AST.GenerateSm
+ genLastCell entity [startVal, inVec, resVal] = cellGn
+ where
+ len = (tfvec_len . Var.varType) inVec
+ cellLabel = mkVHDLExtId "lastCell"
+ cellGenScheme = AST.IfGn ((AST.PrimName $ AST.NSimple nPar) AST.:=: (AST.PrimLit $ show (len-1)))
+ nPar = AST.unsafeVHDLBasicId "n"
+ -- Get the entity name and port names
+ entity_id = ent_id entity
+ argports = map (Monad.liftM fst) (ent_args entity)
+ resport = (Monad.liftM fst) (ent_res entity)
+ -- Assign the ports
+ inport1 = mkAssocElemIndexed (argports!!0) "tmp" (AST.unsafeVHDLBasicId "n-1")
+ inport2 = mkAssocElemIndexed (argports!!1) (varToString inVec) nPar
+ outport = mkAssocElemIndexed resport "tmp" nPar
+ clk_port = mkAssocElem (Just $ mkVHDLExtId "clk") "clk"
+ portassigns = Maybe.catMaybes [inport1,inport2,outport,clk_port]
+ -- Generate the portmap
+ mapLabel = "cell" ++ (AST.fromVHDLId entity_id)
+ compins = mkComponentInst mapLabel entity_id portassigns
+ -- Generate the output assignment
+ assign = mkUncondAssign (Left resVal) (AST.PrimName (AST.NIndexed (AST.IndexedName
+ (AST.NSimple (mkVHDLExtId "tmp")) [AST.PrimLit $ show (len-1)])))
+ -- Return the generate functions
+ cellGn = AST.GenerateSm cellLabel cellGenScheme [] [compins,assign]
+