Generate VHDL signals for internal signals and state.
authorMatthijs Kooijman <m.kooijman@student.utwente.nl>
Tue, 17 Feb 2009 16:13:53 +0000 (17:13 +0100)
committerMatthijs Kooijman <m.kooijman@student.utwente.nl>
Tue, 17 Feb 2009 16:13:53 +0000 (17:13 +0100)
commite479bd172f803b7f75b0dc6b08d3d1792638a711
tree7dc80e39cded574aa2f80cf9a64708bb6c78d3e5
parentc9878e08917311385ce7edbb93f548788cf9df14
Generate VHDL signals for internal signals and state.
VHDL.hs