Ignore cast expressions when generating VHDL.
authorMatthijs Kooijman <m.kooijman@student.utwente.nl>
Tue, 23 Jun 2009 12:54:24 +0000 (14:54 +0200)
committerMatthijs Kooijman <m.kooijman@student.utwente.nl>
Tue, 23 Jun 2009 12:54:24 +0000 (14:54 +0200)
commitc38002cdfd1ec55ffcd6661d7ac2d6c44d220d87
treea905a18e35d44dfc258b63d71e7959e605226995
parent019e55a763768d778d0e62b4dc5e49f3c7e06a0f
Ignore cast expressions when generating VHDL.
VHDL.hs