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(parent: 0332119) | patch
Always add a clk port map on instantiations.
authorMatthijs Kooijman <m.kooijman@student.utwente.nl>
Tue, 23 Jun 2009 10:53:47 +0000 (12:53 +0200)
committerMatthijs Kooijman <m.kooijman@student.utwente.nl>
Tue, 23 Jun 2009 10:53:47 +0000 (12:53 +0200)
commitb4b8def2facb3d3bf92ee02a499405efdf986324
treeb607cb2379bd53aed7b41597f283ead45a036663tree | snapshot
parent0332119bc5f9fed72e7377a11bc21ba885df398ecommit | diff
Always add a clk port map on instantiations.

This changes make the translator generate synthesizable VHDL again.
VHDL.hs diff | blob | history
The Cλash compiler