Add predicates for testing representability of types.
authorMatthijs Kooijman <m.kooijman@student.utwente.nl>
Fri, 3 Jul 2009 16:33:46 +0000 (18:33 +0200)
committerMatthijs Kooijman <m.kooijman@student.utwente.nl>
Fri, 3 Jul 2009 16:33:46 +0000 (18:33 +0200)
commit8153abb4f08f21e097eca9bd38fa6155675be40b
tree5b11d31a1ee20644dbef8aa96abf4f0225eccaa4
parent6fcd2ccf28d4b34eca94eb868ecac83cc5a2c144
Add predicates for testing representability of types.

These predicates try to build a VHDL type from a Core Type, to see if it
will be representable in hardware.
NormalizeTools.hs
VHDLTools.hs