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(parent: e479bd1) | patch
Don't generate ports for non-port signals.
authorMatthijs Kooijman <m.kooijman@student.utwente.nl>
Tue, 17 Feb 2009 16:36:27 +0000 (17:36 +0100)
committerMatthijs Kooijman <m.kooijman@student.utwente.nl>
Tue, 17 Feb 2009 16:37:30 +0000 (17:37 +0100)
commit7bb29e6c00a94229f48663afb6e128d24b3ad7f9
tree7b4a374bcfd15e82852bc49dec18e908002d5ad2tree | snapshot
parente479bd172f803b7f75b0dc6b08d3d1792638a711commit | diff
Don't generate ports for non-port signals.

This allows an entry in a VHDLSignalmap to be empty, which allows for
arguments and results that do not expand into a port, such as state.
Translator.hs diff | blob | history
VHDL.hs diff | blob | history
VHDLTypes.hs diff | blob | history
The Cλash compiler