Generate dummy component instantiations for each architecture.
authorMatthijs Kooijman <m.kooijman@student.utwente.nl>
Fri, 13 Feb 2009 14:12:21 +0000 (15:12 +0100)
committerMatthijs Kooijman <m.kooijman@student.utwente.nl>
Fri, 13 Feb 2009 14:12:21 +0000 (15:12 +0100)
commit7ab181699998f86de0a079ec7a63f7e61ec95cb9
tree940e071804d0378f498d429b284e8c6c16cfc702
parent472a96af53dd624ba526ab86f250ac8f88a152ef
Generate dummy component instantiations for each architecture.

We don't have a session available, so we can't lookup or generate any
names yet. Also, the portmaps are not implemented yet.
VHDL.hs