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Generate a VHDL architecture for each function.
authorMatthijs Kooijman <m.kooijman@student.utwente.nl>
Fri, 13 Feb 2009 13:45:05 +0000 (14:45 +0100)
committerMatthijs Kooijman <m.kooijman@student.utwente.nl>
Fri, 13 Feb 2009 13:45:05 +0000 (14:45 +0100)
commit7a5b4eb318626f327dd6b0d69e99a8247f56399c
tree1d139241f279eabc30e49c38ae4bf6c2a8e5945etree | snapshot
parent4c4b23981da0a67031547c8ff7e4b2a43698dd46commit | diff
Generate a VHDL architecture for each function.

The architecture contains signal declarations, but no instantiations yet.
Pretty.hs diff | blob | history
Translator.hs diff | blob | history
TranslatorTypes.hs diff | blob | history
VHDL.hs diff | blob | history
The Cλash compiler