projects / matthijs / master-project / cλash.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: 9974312) | patch
Use ForSyDe.Backend.VHDL modules to generate VHDL.
authorMatthijs Kooijman <m.kooijman@student.utwente.nl>
Thu, 22 Jan 2009 15:33:44 +0000 (16:33 +0100)
committerMatthijs Kooijman <m.kooijman@student.utwente.nl>
Thu, 22 Jan 2009 16:17:55 +0000 (17:17 +0100)
commit5915de9ec972ca50bd9eb111cddc0fc55aff51ac
treec80db4f3299bee7a0c44885699cb5ef8de19d263tree | snapshot
parent997431255f0345a9785a762fe6193751fae90651commit | diff
Use ForSyDe.Backend.VHDL modules to generate VHDL.

The current code is still a bit hacky, but no longer contains hardcoded
VHDL and instead builds a VHDL AST which is then printed by modules from
ForSyDe.

Note that this uses internal ForSyDe modules. ForSyDe was modified to
expose these internal modules.
Translator.hs diff | blob | history
The Cλash compiler