Add automated testbench generation according to supplied test input
authorChristiaan Baaij <christiaan.baaij@gmail.com>
Tue, 28 Jul 2009 14:52:18 +0000 (16:52 +0200)
committerChristiaan Baaij <christiaan.baaij@gmail.com>
Tue, 28 Jul 2009 14:52:18 +0000 (16:52 +0200)
commit4c63601269c7097e2177c547dc36d4edecc1c648
tree59fa422213bd5e089692e70bbf59cf3261224ec4
parentd30d9fe36698d9d9b5e44099fba9ba090e54064f
Add automated testbench generation according to supplied test input

Will not compile in VHDL yet as we need to implement the VHDL show method first
HighOrdAlu.hs
cλash-nolibdir/clash-nolibdir.cabal
cλash/CLasH/Normalize.hs
cλash/CLasH/Normalize/NormalizeTools.hs
cλash/CLasH/Translator.hs
cλash/CLasH/Translator/Annotations.hs
cλash/CLasH/Utils/Core/CoreTools.hs
cλash/CLasH/VHDL.hs
cλash/CLasH/VHDL/Constants.hs
cλash/clash.cabal