Add port declarations to the VHDL entities.
authorMatthijs Kooijman <m.kooijman@student.utwente.nl>
Fri, 13 Feb 2009 13:07:06 +0000 (14:07 +0100)
committerMatthijs Kooijman <m.kooijman@student.utwente.nl>
Fri, 13 Feb 2009 13:07:06 +0000 (14:07 +0100)
commit4c4b23981da0a67031547c8ff7e4b2a43698dd46
tree7d91aacf48f8b468f224b8a16ae503c4887acfea
parenta8d7c5bd4b745860f321d4315bff0b9efa3cb05c
Add port declarations to the VHDL entities.
VHDL.hs