Allow for generating VHDL for stateless functions.
authorMatthijs Kooijman <m.kooijman@student.utwente.nl>
Tue, 3 Mar 2009 08:59:45 +0000 (09:59 +0100)
committerMatthijs Kooijman <m.kooijman@student.utwente.nl>
Tue, 3 Mar 2009 08:59:45 +0000 (09:59 +0100)
commit23f93793c5f5f44f1443493c171a0b98295a1651
tree62534fb91d867c7a8dff1a41b874ee2fff775730
parent93dad0e8b95c29c56b03c556e16b26aadf4e7a40
Allow for generating VHDL for stateless functions.

Previously, the top level function needed to be stateful always. Now, the
makeVHDL function has a Bool argument to specify statefulness.
Translator.hs