Add port maps to component instantiations.
authorMatthijs Kooijman <m.kooijman@student.utwente.nl>
Mon, 16 Feb 2009 12:35:32 +0000 (13:35 +0100)
committerMatthijs Kooijman <m.kooijman@student.utwente.nl>
Mon, 16 Feb 2009 12:35:32 +0000 (13:35 +0100)
commit20fbdf46508998bd11da03f3abd6e8725508b0a1
treee8e767f762fffe89a01e9590ac4b37a3e0cd593c
parentf8f2ec1ccc1821b4b0f0f80d5a28e49b413a6e19
Add port maps to component instantiations.
VHDL.hs