X-Git-Url: https://git.stderr.nl/gitweb?a=blobdiff_plain;f=reducer.lhs;h=03c688c520ac496f98c8657ca05968c9c96658d0;hb=d514bd151f4bd5bbb5ae6828902a778222de9738;hp=cc6d89fb62cc924c201edc33ef78114cfe1ed4e8;hpb=db31ec50d26e4d299f57fe1b15eb60d57ae7d9dd;p=matthijs%2Fmaster-project%2Fhaskell-symposium-talk.git

diff --git a/reducer.lhs b/reducer.lhs
index cc6d89f..03c688c 100644
--- a/reducer.lhs
+++ b/reducer.lhs
@@ -2,27 +2,28 @@
 \frame{
 \frametitle{More than just toys}
 \pause
+\begin{columns}[l]
+\column{0.5\textwidth}
+\begin{figure}
+\includegraphics<2->[width=5.5cm]{reducer}
+\end{figure}
+\column{0.5\textwidth}
 \begin{itemize}
-  \item We designed a reduction circuit in \clash{}\pause
+  \item We implemented a reduction circuit in \clash{}\pause
   \item Simulation results in Haskell match VHDL simulation results\pause
   \item Synthesis completes without errors or warnings\pause
-  \item For the same Virtex-4 FPGA: \pause
-    \begin{itemize}
-      \item Hand coded VHDL design runs at 200 MHz\pause
-      \item \clash{} design runs at around 85* MHz
-    \end{itemize}
+  \item Around half speed of handcoded and optimized VHDL
 \end{itemize}
-\vspace{6em}
-\uncover<7->{\scriptsize{*Guestimate: design synthesized at 105 MHz, but with an Integer datapath instead of a floating point datapath.}}
+\end{columns}
 }\note[itemize]{
 \item Toys like the poly cpu one are good to give a quick demo
 \item But we used \clash{} to design 'real' hardware
 \item Reduction circuit sums the numbers in a row of a (sparse) matrix
-\item Nice speed considering we don't optimize for it
+\item Nice speed considering we don't optimize for it (only single example!)
 }
 
-\begin{frame}[plain] 
-   \begin{centering} 
-      \includegraphics[height=\paperheight]{reducerschematic.png} 
-      \end{centering} 
-\end{frame} 
\ No newline at end of file
+% \begin{frame}[plain] 
+%    \begin{centering} 
+%       \includegraphics[height=\paperheight]{reducerschematic.png} 
+%       \end{centering} 
+% \end{frame}