X-Git-Url: https://git.stderr.nl/gitweb?a=blobdiff_plain;f=c%CE%BBash%2FCLasH%2FVHDL.hs;h=fd83899cee622a7ddc501afa598a87cc227e9eac;hb=4ae6d0942205c704ef4c15a8ffd9398fd9f7ca53;hp=ad7b39bce67749789ce382e21c4914814fe1e76f;hpb=1ccb9c8289bfb3c2701bf62435332b4c94b04169;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git

diff --git "a/c\316\273ash/CLasH/VHDL.hs" "b/c\316\273ash/CLasH/VHDL.hs"
index ad7b39b..fd83899 100644
--- "a/c\316\273ash/CLasH/VHDL.hs"
+++ "b/c\316\273ash/CLasH/VHDL.hs"
@@ -103,8 +103,8 @@ createLibraryUnits binds = do
 
 -- | Create an entity for a given function
 createEntity ::
-  (CoreSyn.CoreBndr, CoreSyn.CoreExpr) -- | The function
-  -> VHDLSession AST.EntityDec -- | The resulting entity
+  (CoreSyn.CoreBndr, CoreSyn.CoreExpr) -- ^ The function
+  -> VHDLSession AST.EntityDec -- ^ The resulting entity
 
 createEntity (fname, expr) = do
       -- Strip off lambda's, these will be arguments
@@ -139,12 +139,12 @@ createEntity (fname, expr) = do
         return (id, type_mark)
      )
 
-  -- | Create the VHDL AST for an entity
+-- | Create the VHDL AST for an entity
 createEntityAST ::
-  AST.VHDLId                   -- | The name of the function
-  -> [Port]                    -- | The entity's arguments
-  -> Port                      -- | The entity's result
-  -> AST.EntityDec             -- | The entity with the ent_decl filled in as well
+  AST.VHDLId                   -- ^ The name of the function
+  -> [Port]                    -- ^ The entity's arguments
+  -> Port                      -- ^ The entity's result
+  -> AST.EntityDec             -- ^ The entity with the ent_decl filled in as well
 
 createEntityAST vhdl_id args res =
   AST.EntityDec vhdl_id ports
@@ -158,9 +158,9 @@ createEntityAST vhdl_id args res =
 
 -- | Create a port declaration
 mkIfaceSigDec ::
-  AST.Mode                         -- | The mode for the port (In / Out)
-  -> (AST.VHDLId, AST.TypeMark)    -- | The id and type for the port
-  -> AST.IfaceSigDec               -- | The resulting port declaration
+  AST.Mode                         -- ^ The mode for the port (In / Out)
+  -> (AST.VHDLId, AST.TypeMark)    -- ^ The id and type for the port
+  -> AST.IfaceSigDec               -- ^ The resulting port declaration
 
 mkIfaceSigDec mode (id, ty) = AST.IfaceSigDec id mode ty
 
@@ -240,15 +240,6 @@ getSignalId info =
     (error $ "Unnamed signal? This should not happen!")
     (sigName info)
 -}
-   
-mkSigDec :: CoreSyn.CoreBndr -> VHDLSession (Maybe AST.SigDec)
-mkSigDec bndr =
-  if True then do --isInternalSigUse use || isStateSigUse use then do
-    let error_msg = "\nVHDL.mkSigDec: Can not make signal declaration for type: \n" ++ pprString bndr 
-    type_mark <- MonadState.lift vsType $ vhdl_ty error_msg (Var.varType bndr)
-    return $ Just (AST.SigDec (varToVHDLId bndr) type_mark Nothing)
-  else
-    return Nothing
 
 -- | Transforms a core binding into a VHDL concurrent statement
 mkConcSm ::