X-Git-Url: https://git.stderr.nl/gitweb?a=blobdiff_plain;f=c%CE%BBash%2FCLasH%2FVHDL%2FVHDLTypes.hs;h=e95a0c6eac6af1bbd8fe948fc8e769079f82d2e4;hb=fa753965066cadf521a61be8cd052e410c5e4a81;hp=fbdf4d72932b37daedca11af577526226dec7de8;hpb=e90120ffb6999ad931a06fd6c0a3b071408d5945;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git

diff --git "a/c\316\273ash/CLasH/VHDL/VHDLTypes.hs" "b/c\316\273ash/CLasH/VHDL/VHDLTypes.hs"
index fbdf4d7..e95a0c6 100644
--- "a/c\316\273ash/CLasH/VHDL/VHDLTypes.hs"
+++ "b/c\316\273ash/CLasH/VHDL/VHDLTypes.hs"
@@ -27,7 +27,7 @@ type Port = (AST.VHDLId, AST.TypeMark)
 data Entity = Entity { 
   ent_id     :: AST.VHDLId, -- ^ The id of the entity
   ent_args   :: [Port], -- ^ A port for each non-empty function argument
-  ent_res    :: Port, -- ^ The output port
+  ent_res    :: Maybe Port, -- ^ The output port
   ent_dec    :: AST.EntityDec -- ^ The complete entity declaration
 } deriving (Show);