X-Git-Url: https://git.stderr.nl/gitweb?a=blobdiff_plain;f=c%CE%BBash%2FCLasH%2FVHDL%2FVHDLTypes.hs;h=38ccc97f875d6de3e32e3d6939d0459eb3e412b3;hb=75978cf28a619d14ae27ea2bb4a53246b6a0bcd8;hp=fbdf4d72932b37daedca11af577526226dec7de8;hpb=e90120ffb6999ad931a06fd6c0a3b071408d5945;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git

diff --git "a/c\316\273ash/CLasH/VHDL/VHDLTypes.hs" "b/c\316\273ash/CLasH/VHDL/VHDLTypes.hs"
index fbdf4d7..38ccc97 100644
--- "a/c\316\273ash/CLasH/VHDL/VHDLTypes.hs"
+++ "b/c\316\273ash/CLasH/VHDL/VHDLTypes.hs"
@@ -1,23 +1,11 @@
 --
 -- Some types used by the VHDL module.
 --
-{-# LANGUAGE TemplateHaskell #-}
 module CLasH.VHDL.VHDLTypes where
 
--- Standard imports
-import qualified Control.Monad.Trans.State as State
-import qualified Data.Map as Map
-import Data.Accessor
-import qualified Data.Accessor.Template
-
--- GHC API imports
-import qualified HscTypes
-
--- ForSyDe imports
+-- VHDL imports
 import qualified Language.VHDL.AST as AST
 
--- Local imports
-
 -- A description of a port of an entity
 type Port = (AST.VHDLId, AST.TypeMark)
 
@@ -27,7 +15,7 @@ type Port = (AST.VHDLId, AST.TypeMark)
 data Entity = Entity { 
   ent_id     :: AST.VHDLId, -- ^ The id of the entity
   ent_args   :: [Port], -- ^ A port for each non-empty function argument
-  ent_res    :: Port, -- ^ The output port
+  ent_res    :: Maybe Port, -- ^ The output port
   ent_dec    :: AST.EntityDec -- ^ The complete entity declaration
 } deriving (Show);