X-Git-Url: https://git.stderr.nl/gitweb?a=blobdiff_plain;f=c%CE%BBash%2FCLasH%2FVHDL%2FTestbench.hs;h=b7f281b7fec00c6f7599b427713cb444258cb69f;hb=4a1b18cd81cebb66c95cc0ca8a6aaa441bee1418;hp=76fc0739f5d21537575c76d0d3a703d5beae76a3;hpb=0a090d8e4aa17d6f55f94af75972d77f0f963a99;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git

diff --git "a/c\316\273ash/CLasH/VHDL/Testbench.hs" "b/c\316\273ash/CLasH/VHDL/Testbench.hs"
index 76fc073..b7f281b 100644
--- "a/c\316\273ash/CLasH/VHDL/Testbench.hs"
+++ "b/c\316\273ash/CLasH/VHDL/Testbench.hs"
@@ -1,4 +1,3 @@
--- 
 -- Functions to create a VHDL testbench from a list of test input.
 --
 module CLasH.VHDL.Testbench where
@@ -75,7 +74,7 @@ createTestbenchArch mCycles stimuli top testent= do
                     [AST.SigDec clockId std_logicTM (Just $ AST.PrimLit "'0'"),
                      AST.SigDec resetId std_logicTM (Just $ AST.PrimLit "'0'")]
   let oDecs   = AST.SigDec (fst oIface) (snd oIface) Nothing
-  let portmaps = mkAssocElems (map idToVHDLExpr iIds) (AST.NSimple oId) signature
+  portmaps <- mkAssocElems (map idToVHDLExpr iIds) (AST.NSimple oId) signature
   let mIns    = mkComponentInst "totest" entId portmaps
   (stimuliAssigns, stimuliDecs, cycles, used) <- createStimuliAssigns mCycles stimuli (head iIds)
   let finalAssigns = (AST.CSSASm (AST.NSimple resetId AST.:<==: