X-Git-Url: https://git.stderr.nl/gitweb?a=blobdiff_plain;f=c%CE%BBash%2FCLasH%2FVHDL%2FTestbench.hs;h=b7f281b7fec00c6f7599b427713cb444258cb69f;hb=4a1b18cd81cebb66c95cc0ca8a6aaa441bee1418;hp=3f77b78aeb0c93b87cab4706b9fdbe881cb921af;hpb=a8bd9c0833fcf1212f5843b9db6c754cd1086353;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git

diff --git "a/c\316\273ash/CLasH/VHDL/Testbench.hs" "b/c\316\273ash/CLasH/VHDL/Testbench.hs"
index 3f77b78..b7f281b 100644
--- "a/c\316\273ash/CLasH/VHDL/Testbench.hs"
+++ "b/c\316\273ash/CLasH/VHDL/Testbench.hs"
@@ -1,4 +1,3 @@
--- 
 -- Functions to create a VHDL testbench from a list of test input.
 --
 module CLasH.VHDL.Testbench where
@@ -41,7 +40,7 @@ createTestbench mCycles stimuli top = do
   bndr <- mkInternalVar "testbench" TysWiredIn.unitTy
   let entity = createTestbenchEntity bndr
   modA tsEntities (Map.insert bndr entity)
-  arch <- createTestbenchArch mCycles stimuli' top
+  arch <- createTestbenchArch mCycles stimuli' top entity
   modA tsArchitectures (Map.insert bndr arch)
   return bndr
 
@@ -60,9 +59,10 @@ createTestbenchArch ::
   Maybe Int -- ^ Number of cycles to simulate
   -> [CoreSyn.CoreExpr] -- ^ Imput stimuli
   -> CoreSyn.CoreBndr -- ^ Top Entity
+  -> Entity -- ^ The signature to create an architecture for
   -> TranslatorSession (Architecture, [CoreSyn.CoreBndr])
   -- ^ The architecture and any other entities used.
-createTestbenchArch mCycles stimuli top = do
+createTestbenchArch mCycles stimuli top testent= do
   signature <- getEntity top
   let entId   = ent_id signature
       iIface  = ent_args signature
@@ -74,7 +74,7 @@ createTestbenchArch mCycles stimuli top = do
                     [AST.SigDec clockId std_logicTM (Just $ AST.PrimLit "'0'"),
                      AST.SigDec resetId std_logicTM (Just $ AST.PrimLit "'0'")]
   let oDecs   = AST.SigDec (fst oIface) (snd oIface) Nothing
-  let portmaps = mkAssocElems (map idToVHDLExpr iIds) (AST.NSimple oId) signature
+  portmaps <- mkAssocElems (map idToVHDLExpr iIds) (AST.NSimple oId) signature
   let mIns    = mkComponentInst "totest" entId portmaps
   (stimuliAssigns, stimuliDecs, cycles, used) <- createStimuliAssigns mCycles stimuli (head iIds)
   let finalAssigns = (AST.CSSASm (AST.NSimple resetId AST.:<==:
@@ -85,7 +85,7 @@ createTestbenchArch mCycles stimuli top = do
   let outputProc  = createOutputProc [oId]
   let arch = AST.ArchBody
               (AST.unsafeVHDLBasicId "test")
-              (AST.NSimple $ AST.unsafeIdAppend entId "_tb")
+              (AST.NSimple $ ent_id testent)
               (map AST.BDISD (finalIDecs ++ stimuliDecs ++ [oDecs]))
               (mIns :
                 ( (AST.CSPSm clkProc) : (AST.CSPSm outputProc) : finalAssigns ) )