X-Git-Url: https://git.stderr.nl/gitweb?a=blobdiff_plain;f=c%CE%BBash%2FCLasH%2FVHDL%2FTestbench.hs;h=89988f5372327b0eb675ecbff08d525ea62a4c73;hb=a97a53c406ca4da95059a95a4f3d6452eb87b018;hp=2b31925c655e7bcf731a058948b66cd88f22ffc1;hpb=bfe8487df7ef91568b94e6646bb2f474469fb8c2;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git

diff --git "a/c\316\273ash/CLasH/VHDL/Testbench.hs" "b/c\316\273ash/CLasH/VHDL/Testbench.hs"
index 2b31925..89988f5 100644
--- "a/c\316\273ash/CLasH/VHDL/Testbench.hs"
+++ "b/c\316\273ash/CLasH/VHDL/Testbench.hs"
@@ -7,8 +7,7 @@ module CLasH.VHDL.Testbench where
 import qualified Control.Monad as Monad
 import qualified Maybe
 import qualified Data.Map as Map
-import Data.Accessor
-import qualified Data.Accessor.MonadState as MonadState
+import qualified Data.Accessor.Monad.Trans.State as MonadState
 
 -- ForSyDe
 import qualified Language.VHDL.AST as AST
@@ -42,9 +41,9 @@ createTestbench mCycles cores stimuli top = do
   -- testbench has no outputs and no inputs.
   bndr <- mkInternalVar "testbench" TysWiredIn.unitTy
   let entity = createTestbenchEntity bndr
-  modA tsEntities (Map.insert bndr entity)
+  MonadState.modify tsEntities (Map.insert bndr entity)
   arch <- createTestbenchArch mCycles stimuli' top entity
-  modA tsArchitectures (Map.insert bndr arch)
+  MonadState.modify tsArchitectures (Map.insert bndr arch)
   return bndr
 
 createTestbenchEntity :: 
@@ -118,12 +117,14 @@ createStimuliAssigns mCycles stimuli signal = do
   outps <- mapM (\x -> MonadState.lift tsType (varToVHDLExpr x)) resvars
   let wformelems = zipWith genWformElem [0,10..] outps
   let inassign = AST.CSSASm $ AST.NSimple signal AST.:<==: AST.ConWforms [] (AST.Wform wformelems) Nothing
-  return (stimuli_sms ++ [inassign], sig_decs, inputlen, concat useds)
+  case (concat stimuli_sms) of
+    []        -> return ([inassign], [], inputlen, concat useds)
+    stims     -> return (stims ++ [inassign], sig_decs, inputlen, concat useds)
 
 createStimulans ::
   CoreSyn.CoreExpr -- ^ The stimulans
   -> Int -- ^ The cycle for this stimulans
-  -> TranslatorSession ( AST.ConcSm
+  -> TranslatorSession ( [AST.ConcSm]
                        , Var.Var 
                        , [CoreSyn.CoreBndr]) -- ^ (The statement, the variable it assigns to (assumed to be available!), Any entities used by this stimulans)
 
@@ -137,8 +138,10 @@ createStimulans expr cycl = do
   sig_dec_maybes <- mapM (mkSigDec . fst) (filter ((/=res).fst) binds)
   let sig_decs = map (AST.BDISD) (Maybe.catMaybes $ sig_dec_maybes)
   let block_label = mkVHDLExtId ("testcycle_" ++ (show cycl))
-  let block = AST.BlockSm block_label [] (AST.PMapAspect []) sig_decs (concat stimulansbindss)  
-  return (AST.CSBSm block, res, concat useds)
+  let block = AST.BlockSm block_label [] (AST.PMapAspect []) sig_decs (concat stimulansbindss)
+  case (sig_decs,(concat stimulansbindss)) of
+    ([],[])   ->  return ([], res, concat useds)
+    otherwise ->  return ([AST.CSBSm block], res, concat useds)
  
 -- | generates a clock process with a period of 10ns
 createClkProc :: AST.ProcSm