X-Git-Url: https://git.stderr.nl/gitweb?a=blobdiff_plain;f=c%CE%BBash%2FCLasH%2FVHDL%2FGenerate.hs;h=7c604d6d732f0b7fc8e4997f67dd3fa68b08b059;hb=a54863feb7304aa6a843efc15d29f017c45407f4;hp=dec1b62375a404867ec1c59f7908c2fc3befcd4e;hpb=66ef5bd26b2c02cb12e702c60668294fd80ea8c2;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git diff --git "a/c\316\273ash/CLasH/VHDL/Generate.hs" "b/c\316\273ash/CLasH/VHDL/Generate.hs" index dec1b62..7c604d6 100644 --- "a/c\316\273ash/CLasH/VHDL/Generate.hs" +++ "b/c\316\273ash/CLasH/VHDL/Generate.hs" @@ -44,15 +44,15 @@ getEntity :: getEntity fname = Utils.makeCached fname tsEntities $ do expr <- Normalize.getNormalized fname - -- Strip off lambda's, these will be arguments - let (args, letexpr) = CoreSyn.collectBinders expr + -- Split the normalized expression + let (args, binds, res) = Normalize.splitNormalized expr -- Generate ports for all non-empty types args' <- catMaybesM $ mapM mkMap args - -- There must be a let at top level - let (CoreSyn.Let binds (CoreSyn.Var res)) = letexpr -- TODO: Handle Nothing res' <- mkMap res - let vhdl_id = mkVHDLBasicId $ varToString fname ++ "_" ++ varToStringUniq fname + count <- getA tsEntityCounter + let vhdl_id = mkVHDLBasicId $ varToString fname ++ "Component_" ++ show count + putA tsEntityCounter (count + 1) let ent_decl = createEntityAST vhdl_id args' res' let signature = Entity vhdl_id args' res' ent_decl return signature @@ -90,9 +90,10 @@ createEntityAST vhdl_id args res = -- Create a basic Id, since VHDL doesn't grok filenames with extended Ids. ports = map (mkIfaceSigDec AST.In) args ++ (Maybe.maybeToList res_port) - ++ [clk_port] + ++ [clk_port,resetn_port] -- Add a clk port if we have state clk_port = AST.IfaceSigDec clockId AST.In std_logicTM + resetn_port = AST.IfaceSigDec resetId AST.In std_logicTM res_port = fmap (mkIfaceSigDec AST.Out) res -- | Create a port declaration @@ -111,29 +112,99 @@ getArchitecture :: getArchitecture fname = Utils.makeCached fname tsArchitectures $ do expr <- Normalize.getNormalized fname + -- Split the normalized expression + let (args, binds, res) = Normalize.splitNormalized expr + + -- Get the entity for this function signature <- getEntity fname let entity_id = ent_id signature - -- Strip off lambda's, these will be arguments - let (args, letexpr) = CoreSyn.collectBinders expr - -- There must be a let at top level - let (CoreSyn.Let (CoreSyn.Rec binds) (CoreSyn.Var res)) = letexpr -- Create signal declarations for all binders in the let expression, except -- for the output port (that will already have an output port declared in -- the entity). - sig_dec_maybes <- mapM (mkSigDec' . fst) (filter ((/=res).fst) binds) + sig_dec_maybes <- mapM (mkSigDec . fst) (filter ((/=res).fst) binds) let sig_decs = Maybe.catMaybes $ sig_dec_maybes - - (statementss, used_entitiess) <- Monad.mapAndUnzipM mkConcSm binds - let statements = concat statementss - let used_entities = concat used_entitiess - let arch = AST.ArchBody (mkVHDLBasicId "structural") (AST.NSimple entity_id) (map AST.BDISD sig_decs) (statements ++ procs') + -- Process each bind, resulting in info about state variables and concurrent + -- statements. + (state_vars, sms) <- Monad.mapAndUnzipM dobind binds + let (in_state_maybes, out_state_maybes) = unzip state_vars + let (statementss, used_entitiess) = unzip sms + -- Get initial state, if it's there + initSmap <- getA tsInitStates + let init_state = Map.lookup fname initSmap + -- Create a state proc, if needed + (state_proc, resbndr) <- case (Maybe.catMaybes in_state_maybes, Maybe.catMaybes out_state_maybes, init_state) of + ([in_state], [out_state], Nothing) -> error $ "No initial state defined for: " ++ show fname + ([in_state], [out_state], Just resetval) -> mkStateProcSm (in_state, out_state,resetval) + ([], [], Just _) -> error $ "Initial state defined for state-less function: " ++ show fname + ([], [], Nothing) -> return ([],[]) + (ins, outs, res) -> error $ "Weird use of state in " ++ show fname ++ ". In: " ++ show ins ++ " Out: " ++ show outs + -- Join the create statements and the (optional) state_proc + let statements = concat statementss ++ state_proc + -- Create the architecture + let arch = AST.ArchBody (mkVHDLBasicId "structural") (AST.NSimple entity_id) (map AST.BDISD sig_decs) statements + let used_entities = (concat used_entitiess) ++ resbndr return (arch, used_entities) where - procs = [] --map mkStateProcSm [] -- (makeStatePairs flatfunc) - procs' = map AST.CSPSm procs - -- mkSigDec only uses tsTypes from the state - mkSigDec' = mkSigDec + dobind :: (CoreSyn.CoreBndr, CoreSyn.CoreExpr) -- ^ The bind to process + -> TranslatorSession ((Maybe CoreSyn.CoreBndr, Maybe CoreSyn.CoreBndr), ([AST.ConcSm], [CoreSyn.CoreBndr])) + -- ^ ((Input state variable, output state variable), (statements, used entities)) + -- newtype unpacking is just a cast + dobind (bndr, unpacked@(CoreSyn.Cast packed coercion)) + | hasStateType packed && not (hasStateType unpacked) + = return ((Just bndr, Nothing), ([], [])) + -- With simplCore, newtype packing is just a cast + dobind (bndr, packed@(CoreSyn.Cast unpacked@(CoreSyn.Var state) coercion)) + | hasStateType packed && not (hasStateType unpacked) + = return ((Nothing, Just state), ([], [])) + -- Without simplCore, newtype packing uses a data constructor + dobind (bndr, (CoreSyn.App (CoreSyn.App (CoreSyn.Var con) (CoreSyn.Type _)) (CoreSyn.Var state))) + | isStateCon con + = return ((Nothing, Just state), ([], [])) + -- Anything else is handled by mkConcSm + dobind bind = do + sms <- mkConcSm bind + return ((Nothing, Nothing), sms) + +mkStateProcSm :: + (CoreSyn.CoreBndr, CoreSyn.CoreBndr, CoreSyn.CoreBndr) -- ^ The current state, new state and reset variables + -> TranslatorSession ([AST.ConcSm], [CoreSyn.CoreBndr]) -- ^ The resulting statements +mkStateProcSm (old, new, res) = do + nonempty <- hasNonEmptyType old + if nonempty + then do + let error_msg = "\nVHDL.mkSigDec: Can not make signal declaration for type: \n" ++ pprString res + type_mark_old_maybe <- MonadState.lift tsType $ vhdl_ty error_msg (Var.varType old) + let type_mark_old = Maybe.fromJust type_mark_old_maybe + type_mark_res_maybe <- MonadState.lift tsType $ vhdl_ty error_msg (Var.varType res) + let type_mark_res' = Maybe.fromJust type_mark_res_maybe + let type_mark_res = if type_mark_old == type_mark_res' then + type_mark_res' + else + error $ "Initial state has different type than state type, state type: " ++ show type_mark_old ++ ", init type: " ++ show type_mark_res' + let resvalid = mkVHDLBasicId $ varToString res ++ "val" + let resvaldec = AST.BDISD $ AST.SigDec resvalid type_mark_res Nothing + let reswform = AST.Wform [AST.WformElem (AST.PrimName $ AST.NSimple resvalid) Nothing] + let res_assign = AST.SigAssign (varToVHDLName old) reswform + let blocklabel = mkVHDLBasicId $ "state" + let statelabel = mkVHDLBasicId $ "stateupdate" + let rising_edge = AST.NSimple $ mkVHDLBasicId "rising_edge" + let wform = AST.Wform [AST.WformElem (AST.PrimName $ varToVHDLName new) Nothing] + let clk_assign = AST.SigAssign (varToVHDLName old) wform + let rising_edge_clk = AST.PrimFCall $ AST.FCall rising_edge [Nothing AST.:=>: (AST.ADName $ AST.NSimple clockId)] + let resetn_is_low = (AST.PrimName $ AST.NSimple resetId) AST.:=: (AST.PrimLit "'0'") + signature <- getEntity res + let entity_id = ent_id signature + let reslabel = "resetval_" ++ ((prettyShow . varToVHDLName) res) + let portmaps = mkAssocElems [] (AST.NSimple resvalid) signature + let reset_statement = mkComponentInst reslabel entity_id portmaps + let clk_statement = [AST.ElseIf rising_edge_clk [clk_assign]] + let statement = AST.IfSm resetn_is_low [res_assign] clk_statement Nothing + let stateupdate = AST.CSPSm $ AST.ProcSm statelabel [clockId,resetId] [statement] + let block = AST.CSBSm $ AST.BlockSm blocklabel [] (AST.PMapAspect []) [resvaldec] [reset_statement,stateupdate] + return ([block],[res]) + else + return ([],[]) -- | Transforms a core binding into a VHDL concurrent statement mkConcSm :: @@ -144,7 +215,10 @@ mkConcSm :: -- Ignore Cast expressions, they should not longer have any meaning as long as --- the type works out. +-- the type works out. Throw away state repacking +mkConcSm (bndr, to@(CoreSyn.Cast from ty)) + | hasStateType to && hasStateType from + = return ([],[]) mkConcSm (bndr, CoreSyn.Cast expr ty) = mkConcSm (bndr, expr) -- Simple a = b assignments are just like applications, but without arguments. @@ -158,7 +232,7 @@ mkConcSm (bndr, app@(CoreSyn.App _ _))= do let valargs = get_val_args (Var.varType f) args genApplication (Left bndr) f (map Left valargs) --- A single alt case must be a selector. This means thee scrutinee is a simple +-- A single alt case must be a selector. This means the scrutinee is a simple -- variable, the alternative is a dataalt with a single non-wild binder that -- is also returned. mkConcSm (bndr, expr@(CoreSyn.Case (CoreSyn.Var scrut) b ty [alt])) @@ -183,14 +257,23 @@ mkConcSm (bndr, expr@(CoreSyn.Case (CoreSyn.Var scrut) b ty [alt])) -- binders in the alts and only variables in the case values and a variable -- for a scrutinee. We check the constructor of the second alt, since the -- first is the default case, if there is any. -mkConcSm (bndr, (CoreSyn.Case (CoreSyn.Var scrut) b ty [(_, _, CoreSyn.Var false), (con, _, CoreSyn.Var true)])) = do + +-- mkConcSm (bndr, (CoreSyn.Case (CoreSyn.Var scrut) b ty [(_, _, CoreSyn.Var false), (con, _, CoreSyn.Var true)])) = do +-- scrut' <- MonadState.lift tsType $ varToVHDLExpr scrut +-- altcon <- MonadState.lift tsType $ altconToVHDLExpr con +-- let cond_expr = scrut' AST.:=: altcon +-- true_expr <- MonadState.lift tsType $ varToVHDLExpr true +-- false_expr <- MonadState.lift tsType $ varToVHDLExpr false +-- return ([mkCondAssign (Left bndr) cond_expr true_expr false_expr], []) +mkConcSm (bndr, (CoreSyn.Case (CoreSyn.Var scrut) _ _ (alt:alts))) = do --error "\nVHDL.mkConcSm: Not in normal form: Case statement with more than two alternatives" scrut' <- MonadState.lift tsType $ varToVHDLExpr scrut - let cond_expr = scrut' AST.:=: (altconToVHDLExpr con) - true_expr <- MonadState.lift tsType $ varToVHDLExpr true - false_expr <- MonadState.lift tsType $ varToVHDLExpr false - return ([mkCondAssign (Left bndr) cond_expr true_expr false_expr], []) + -- Omit first condition, which is the default + altcons <- MonadState.lift tsType $ mapM (altconToVHDLExpr . (\(con,_,_) -> con)) alts + let cond_exprs = map (\x -> scrut' AST.:=: x) altcons + -- Rotate expressions to the left, so that the expression related to the default case is the last + exprs <- MonadState.lift tsType $ mapM (varToVHDLExpr . (\(_,_,CoreSyn.Var expr) -> expr)) (alts ++ [alt]) + return ([mkAltsAssign (Left bndr) cond_exprs exprs], []) -mkConcSm (_, (CoreSyn.Case (CoreSyn.Var _) _ _ alts)) = error "\nVHDL.mkConcSm: Not in normal form: Case statement with more than two alternatives" mkConcSm (_, CoreSyn.Case _ _ _ _) = error "\nVHDL.mkConcSm: Not in normal form: Case statement has does not have a simple variable as scrutinee" mkConcSm (bndr, expr) = error $ "\nVHDL.mkConcSM: Unsupported binding in let expression: " ++ pprString bndr ++ " = " ++ pprString expr @@ -243,14 +326,16 @@ genVarArgs wrap dst func args = wrap dst func args' -- | A function to wrap a builder-like function that expects its arguments to -- be Literals genLitArgs :: - (dst -> func -> [Literal.Literal] -> res) - -> (dst -> func -> [Either CoreSyn.CoreExpr AST.Expr] -> res) -genLitArgs wrap dst func args = wrap dst func args' - where - args' = map exprToLit litargs - -- FIXME: Check if we were passed an CoreSyn.App - litargs = concat (map getLiterals exprargs) - (exprargs, []) = Either.partitionEithers args + (dst -> func -> [Literal.Literal] -> TranslatorSession [AST.ConcSm]) + -> (dst -> func -> [Either CoreSyn.CoreExpr AST.Expr] -> TranslatorSession [AST.ConcSm]) +genLitArgs wrap dst func args = do + hscenv <- MonadState.lift tsType $ getA tsHscEnv + let (exprargs, []) = Either.partitionEithers args + -- FIXME: Check if we were passed an CoreSyn.App + let litargs = concat (map (getLiterals hscenv) exprargs) + let args' = map exprToLit litargs + concsms <- wrap dst func args' + return concsms -- | A function to wrap a builder-like function that produces an expression -- and expects it to be assigned to the destination. @@ -285,7 +370,7 @@ genNegation' _ f [arg] = do let name = Name.getOccString (TyCon.tyConName tycon) case name of "SizedInt" -> return $ AST.Neg arg1 - otherwise -> error $ "\nGenerate.genNegation': Negation allowed for type: " ++ show name + otherwise -> error $ "\nGenerate.genNegation': Negation not allowed for type: " ++ show name -- | Generate a function call from the destination binder, function name and a -- list of expressions (its arguments) @@ -301,12 +386,13 @@ genFCall' switch (Left res) f args = do genFCall' _ (Right name) _ _ = error $ "\nGenerate.genFCall': Cannot generate builtin function call assigned to a VHDLName: " ++ show name genFromSizedWord :: BuiltinBuilder -genFromSizedWord = genNoInsts $ genExprArgs $ genExprRes genFromSizedWord' -genFromSizedWord' :: Either CoreSyn.CoreBndr AST.VHDLName -> CoreSyn.CoreBndr -> [AST.Expr] -> TranslatorSession AST.Expr -genFromSizedWord' (Left res) f args = do - let fname = varToString f - return $ AST.PrimFCall $ AST.FCall (AST.NSimple (mkVHDLBasicId toIntegerId)) $ - map (\exp -> Nothing AST.:=>: AST.ADExpr exp) args +genFromSizedWord = genNoInsts $ genExprArgs genFromSizedWord' +genFromSizedWord' :: Either CoreSyn.CoreBndr AST.VHDLName -> CoreSyn.CoreBndr -> [AST.Expr] -> TranslatorSession [AST.ConcSm] +genFromSizedWord' (Left res) f args@[arg] = do + return $ [mkUncondAssign (Left res) arg] + -- let fname = varToString f + -- return $ AST.PrimFCall $ AST.FCall (AST.NSimple (mkVHDLBasicId toIntegerId)) $ + -- map (\exp -> Nothing AST.:=>: AST.ADExpr exp) args genFromSizedWord' (Right name) _ _ = error $ "\nGenerate.genFromSizedWord': Cannot generate builtin function call assigned to a VHDLName: " ++ show name genResize :: BuiltinBuilder @@ -335,17 +421,17 @@ genFromInteger' (Left res) f lits = do { ; (tycon, args) = Type.splitTyConApp ty ; name = Name.getOccString (TyCon.tyConName tycon) } ; - ; case name of - "RangedWord" -> return $ AST.PrimLit (show (last lits)) - otherwise -> do { - ; len <- case name of - "SizedInt" -> MonadState.lift tsType $ tfp_to_int (sized_int_len_ty ty) - "SizedWord" -> MonadState.lift tsType $ tfp_to_int (sized_word_len_ty ty) - "RangedWord" -> MonadState.lift tsType $ tfp_to_int (ranged_word_bound_ty ty) - ; let fname = case name of "SizedInt" -> toSignedId ; "SizedWord" -> toUnsignedId - ; return $ AST.PrimFCall $ AST.FCall (AST.NSimple (mkVHDLBasicId fname)) - [Nothing AST.:=>: AST.ADExpr (AST.PrimLit (show (last lits))), Nothing AST.:=>: AST.ADExpr( AST.PrimLit (show len))] + ; len <- case name of + "SizedInt" -> MonadState.lift tsType $ tfp_to_int (sized_int_len_ty ty) + "SizedWord" -> MonadState.lift tsType $ tfp_to_int (sized_word_len_ty ty) + "RangedWord" -> do { + ; bound <- MonadState.lift tsType $ tfp_to_int (ranged_word_bound_ty ty) + ; return $ floor (logBase 2 (fromInteger (toInteger (bound)))) + 1 } + ; let fname = case name of "SizedInt" -> toSignedId ; "SizedWord" -> toUnsignedId ; "RangedWord" -> toUnsignedId + ; return $ AST.PrimFCall $ AST.FCall (AST.NSimple (mkVHDLBasicId fname)) + [Nothing AST.:=>: AST.ADExpr (AST.PrimLit (show (last lits))), Nothing AST.:=>: AST.ADExpr( AST.PrimLit (show len))] + } genFromInteger' (Right name) _ _ = error $ "\nGenerate.genFromInteger': Cannot generate builtin function call assigned to a VHDLName: " ++ show name @@ -605,6 +691,34 @@ genZip' (Left res) f args@[arg1, arg2] = do { -- Return the generate functions ; return [AST.CSGSm $ AST.GenerateSm label genScheme [] [resA_assign,resB_assign]] } + +-- | Generate a generate statement for the builtin function "fst" +genFst :: BuiltinBuilder +genFst = genNoInsts $ genVarArgs genFst' +genFst' :: (Either CoreSyn.CoreBndr AST.VHDLName) -> CoreSyn.CoreBndr -> [Var.Var] -> TranslatorSession [AST.ConcSm] +genFst' (Left res) f args@[arg] = do { + ; labels <- MonadState.lift tsType $ getFieldLabels (Var.varType arg) + ; let { argexpr' = varToVHDLName arg + ; argexprA = vhdlNameToVHDLExpr $ mkSelectedName argexpr' (labels!!0) + ; assign = mkUncondAssign (Left res) argexprA + } ; + -- Return the generate functions + ; return [assign] + } + +-- | Generate a generate statement for the builtin function "snd" +genSnd :: BuiltinBuilder +genSnd = genNoInsts $ genVarArgs genSnd' +genSnd' :: (Either CoreSyn.CoreBndr AST.VHDLName) -> CoreSyn.CoreBndr -> [Var.Var] -> TranslatorSession [AST.ConcSm] +genSnd' (Left res) f args@[arg] = do { + ; labels <- MonadState.lift tsType $ getFieldLabels (Var.varType arg) + ; let { argexpr' = varToVHDLName arg + ; argexprB = vhdlNameToVHDLExpr $ mkSelectedName argexpr' (labels!!1) + ; assign = mkUncondAssign (Left res) argexprB + } ; + -- Return the generate functions + ; return [assign] + } -- | Generate a generate statement for the builtin function "unzip" genUnzip :: BuiltinBuilder @@ -768,7 +882,68 @@ genIterateOrGenerate'' len iter (Left res) f [app_f, start] = do -- Return the conditional generate part return $ (AST.GenerateSm cond_label cond_scheme [] app_concsms, used) - +genBlockRAM :: BuiltinBuilder +genBlockRAM = genNoInsts $ genExprArgs genBlockRAM' + +genBlockRAM' :: (Either CoreSyn.CoreBndr AST.VHDLName) -> CoreSyn.CoreBndr -> [AST.Expr] -> TranslatorSession [AST.ConcSm] +genBlockRAM' (Left res) f args@[data_in,rdaddr,wraddr,wrenable] = do + -- Get the ram type + let (tup,data_out) = Type.splitAppTy (Var.varType res) + let (tup',ramvec) = Type.splitAppTy tup + let Just realram = Type.coreView ramvec + let Just (tycon, types) = Type.splitTyConApp_maybe realram + Just ram_vhdl_ty <- MonadState.lift tsType $ vhdl_ty "wtf" (head types) + -- Make the intermediate vector + let ram_dec = AST.BDISD $ AST.SigDec ram_id ram_vhdl_ty Nothing + -- Get the data_out name + reslabels <- MonadState.lift tsType $ getFieldLabels (Var.varType res) + let resname' = varToVHDLName res + let resname = mkSelectedName resname' (reslabels!!0) + let rdaddr_int = genExprFCall (mkVHDLBasicId toIntegerId) rdaddr + let argexpr = vhdlNameToVHDLExpr $ mkIndexedName (AST.NSimple ram_id) rdaddr_int + let assign = mkUncondAssign (Right resname) argexpr + let block_label = mkVHDLExtId ("blockRAM" ++ (varToString res)) + let block = AST.BlockSm block_label [] (AST.PMapAspect []) [ram_dec] [assign, mkUpdateProcSm] + return [AST.CSBSm block] + where + ram_id = mkVHDLBasicId "ram" + mkUpdateProcSm :: AST.ConcSm + mkUpdateProcSm = AST.CSPSm $ AST.ProcSm proclabel [clockId] [statement] + where + proclabel = mkVHDLBasicId "updateRAM" + rising_edge = mkVHDLBasicId "rising_edge" + wraddr_int = genExprFCall (mkVHDLBasicId toIntegerId) wraddr + ramloc = mkIndexedName (AST.NSimple ram_id) wraddr_int + wform = AST.Wform [AST.WformElem data_in Nothing] + ramassign = AST.SigAssign ramloc wform + rising_edge_clk = genExprFCall rising_edge (AST.PrimName $ AST.NSimple clockId) + statement = AST.IfSm (AST.And rising_edge_clk wrenable) [ramassign] [] Nothing + +genSplit :: BuiltinBuilder +genSplit = genNoInsts $ genVarArgs genSplit' + +genSplit' :: (Either CoreSyn.CoreBndr AST.VHDLName) -> CoreSyn.CoreBndr -> [Var.Var] -> TranslatorSession [AST.ConcSm] +genSplit' (Left res) f args@[vecIn] = do { + ; labels <- MonadState.lift tsType $ getFieldLabels (Var.varType res) + ; len <- MonadState.lift tsType $ tfp_to_int $ (tfvec_len_ty . Var.varType) vecIn + ; let { block_label = mkVHDLExtId ("split" ++ (varToString vecIn)) + ; halflen = round ((fromIntegral len) / 2) + ; rangeL = vecSlice (AST.PrimLit "0") (AST.PrimLit $ show (halflen - 1)) + ; rangeR = vecSlice (AST.PrimLit $ show halflen) (AST.PrimLit $ show (len - 1)) + ; resname = varToVHDLName res + ; resnameL = mkSelectedName resname (labels!!0) + ; resnameR = mkSelectedName resname (labels!!1) + ; argexprL = vhdlNameToVHDLExpr rangeL + ; argexprR = vhdlNameToVHDLExpr rangeR + ; out_assignL = mkUncondAssign (Right resnameL) argexprL + ; out_assignR = mkUncondAssign (Right resnameR) argexprR + ; block = AST.BlockSm block_label [] (AST.PMapAspect []) [] [out_assignL, out_assignR] + } + ; return [AST.CSBSm block] + } + where + vecSlice init last = AST.NSlice (AST.SliceName (varToVHDLName res) + (AST.ToRange init last)) ----------------------------------------------------------------------------- -- Function to generate VHDL for applications ----------------------------------------------------------------------------- @@ -792,8 +967,8 @@ genApplication dst f args = do let entity_id = ent_id signature -- TODO: Using show here isn't really pretty, but we'll need some -- unique-ish value... - let label = "comp_ins_" ++ (either show prettyShow) dst - portmaps <- mkAssocElems args' ((either varToVHDLName id) dst) signature + let label = "comp_ins_" ++ (either (prettyShow . varToVHDLName) prettyShow) dst + let portmaps = mkAssocElems args' ((either varToVHDLName id) dst) signature return ([mkComponentInst label entity_id portmaps], [f]) False -> do -- Not a top level binder, so this must be a local variable reference. @@ -802,7 +977,7 @@ genApplication dst f args = do -- assignment here. f' <- MonadState.lift tsType $ varToVHDLExpr f return $ ([mkUncondAssign dst f'], []) - True | not stateful -> + True -> case Var.idDetails f of IdInfo.DataConWorkId dc -> case dst of -- It's a datacon. Create a record from its arguments. @@ -852,7 +1027,7 @@ genApplication dst f args = do -- TODO: Using show here isn't really pretty, but we'll need some -- unique-ish value... let label = "comp_ins_" ++ (either show prettyShow) dst - portmaps <- mkAssocElems args' ((either varToVHDLName id) dst) signature + let portmaps = mkAssocElems args' ((either varToVHDLName id) dst) signature return ([mkComponentInst label entity_id portmaps], [f]) False -> do -- Not a top level binder, so this must be a local variable reference. @@ -874,16 +1049,6 @@ genApplication dst f args = do error $ "\nGenerate.genApplication(ClassOpId): Incorrect number of arguments to builtin function: " ++ pprString f ++ " Args: " ++ show args Nothing -> error $ "\nGenerate.genApplication(ClassOpId): Using function from another module that is not a known builtin: " ++ pprString f details -> error $ "\nGenerate.genApplication: Calling unsupported function " ++ pprString f ++ " with GlobalIdDetails " ++ pprString details - -- If we can't generate a component instantiation, and the destination is - -- a state type, don't generate anything. - _ -> return ([], []) - where - -- Is our destination a state value? - stateful = case dst of - -- When our destination is a VHDL name, it won't have had a state type - Right _ -> False - -- Otherwise check its type - Left bndr -> hasStateType bndr ----------------------------------------------------------------------------- -- Functions to generate functions dealing with vectors. @@ -900,7 +1065,7 @@ vectorFunId el_ty fname = do -- the VHDLState or something. let vectorTM = mkVHDLExtId $ "vector_" ++ (AST.fromVHDLId elemTM) typefuns <- getA tsTypeFuns - case Map.lookup (OrdType el_ty, fname) typefuns of + case Map.lookup (StdType $ OrdType el_ty, fname) typefuns of -- Function already generated, just return it Just (id, _) -> return id -- Function not generated yet, generate it @@ -908,7 +1073,7 @@ vectorFunId el_ty fname = do let functions = genUnconsVectorFuns elemTM vectorTM case lookup fname functions of Just body -> do - modA tsTypeFuns $ Map.insert (OrdType el_ty, fname) (function_id, (fst body)) + modA tsTypeFuns $ Map.insert (StdType $ OrdType el_ty, fname) (function_id, (fst body)) mapM_ (vectorFunId el_ty) (snd body) return function_id Nothing -> error $ "\nGenerate.vectorFunId: I don't know how to generate vector function " ++ fname @@ -920,7 +1085,7 @@ genUnconsVectorFuns :: AST.TypeMark -- ^ type of the vector elements -> [(String, (AST.SubProgBody, [String]))] genUnconsVectorFuns elemTM vectorTM = [ (exId, (AST.SubProgBody exSpec [] [exExpr],[])) - , (replaceId, (AST.SubProgBody replaceSpec [AST.SPVD replaceVar] [replaceExpr,replaceRet],[])) + , (replaceId, (AST.SubProgBody replaceSpec [AST.SPVD replaceVar] [replaceExpr1,replaceExpr2,replaceRet],[])) , (lastId, (AST.SubProgBody lastSpec [] [lastExpr],[])) , (initId, (AST.SubProgBody initSpec [AST.SPVD initVar] [initExpr, initRet],[])) , (minimumId, (AST.SubProgBody minimumSpec [] [minimumExpr],[])) @@ -956,12 +1121,11 @@ genUnconsVectorFuns elemTM vectorTM = sPar = AST.unsafeVHDLBasicId "s" resId = AST.unsafeVHDLBasicId "res" exSpec = AST.Function (mkVHDLExtId exId) [AST.IfaceVarDec vecPar vectorTM, - AST.IfaceVarDec ixPar naturalTM] elemTM + AST.IfaceVarDec ixPar unsignedTM] elemTM exExpr = AST.ReturnSm (Just $ AST.PrimName $ AST.NIndexed - (AST.IndexedName (AST.NSimple vecPar) [AST.PrimName $ - AST.NSimple ixPar])) + (AST.IndexedName (AST.NSimple vecPar) [genExprFCall (mkVHDLBasicId toIntegerId) (AST.PrimName $ AST.NSimple $ ixPar)])) replaceSpec = AST.Function (mkVHDLExtId replaceId) [ AST.IfaceVarDec vecPar vectorTM - , AST.IfaceVarDec iPar naturalTM + , AST.IfaceVarDec iPar unsignedTM , AST.IfaceVarDec aPar elemTM ] vectorTM -- variable res : fsvec_x (0 to vec'length-1); @@ -975,13 +1139,8 @@ genUnconsVectorFuns elemTM vectorTM = (AST.PrimLit "1")) ])) Nothing -- res AST.:= vec(0 to i-1) & a & vec(i+1 to length'vec-1) - replaceExpr = AST.NSimple resId AST.:= - (vecSlice (AST.PrimLit "0") (AST.PrimName (AST.NSimple iPar) AST.:-: AST.PrimLit "1") AST.:&: - AST.PrimName (AST.NSimple aPar) AST.:&: - vecSlice (AST.PrimName (AST.NSimple iPar) AST.:+: AST.PrimLit "1") - ((AST.PrimName (AST.NAttribute $ - AST.AttribName (AST.NSimple vecPar) (AST.NSimple $ mkVHDLBasicId lengthId) Nothing)) - AST.:-: AST.PrimLit "1")) + replaceExpr1 = AST.NSimple resId AST.:= AST.PrimName (AST.NSimple vecPar) + replaceExpr2 = AST.NIndexed (AST.IndexedName (AST.NSimple resId) [genExprFCall (mkVHDLBasicId toIntegerId) (AST.PrimName $ AST.NSimple $ iPar)]) AST.:= AST.PrimName (AST.NSimple aPar) replaceRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId) vecSlice init last = AST.PrimName (AST.NSlice (AST.SliceName @@ -1346,15 +1505,28 @@ globalNameTable = Map.fromList , (hwandId , (2, genOperator2 AST.And ) ) , (hworId , (2, genOperator2 AST.Or ) ) , (hwnotId , (1, genOperator1 AST.Not ) ) + , (equalityId , (2, genOperator2 (AST.:=:) ) ) + , (inEqualityId , (2, genOperator2 (AST.:/=:) ) ) + , (ltId , (2, genOperator2 (AST.:<:) ) ) + , (lteqId , (2, genOperator2 (AST.:<=:) ) ) + , (gtId , (2, genOperator2 (AST.:>:) ) ) + , (gteqId , (2, genOperator2 (AST.:>=:) ) ) + , (boolOrId , (2, genOperator2 AST.Or ) ) + , (boolAndId , (2, genOperator2 AST.And ) ) , (plusId , (2, genOperator2 (AST.:+:) ) ) , (timesId , (2, genOperator2 (AST.:*:) ) ) , (negateId , (1, genNegation ) ) , (minusId , (2, genOperator2 (AST.:-:) ) ) , (fromSizedWordId , (1, genFromSizedWord ) ) , (fromIntegerId , (1, genFromInteger ) ) - , (resizeId , (1, genResize ) ) + , (resizeWordId , (1, genResize ) ) + , (resizeIntId , (1, genResize ) ) , (sizedIntId , (1, genSizedInt ) ) , (smallIntegerId , (1, genFromInteger ) ) + , (fstId , (1, genFst ) ) + , (sndId , (1, genSnd ) ) + , (blockRAMId , (5, genBlockRAM ) ) + , (splitId , (1, genSplit ) ) --, (tfvecId , (1, genTFVec ) ) , (minimumId , (2, error $ "\nFunction name: \"minimum\" is used internally, use another name")) ]