X-Git-Url: https://git.stderr.nl/gitweb?a=blobdiff_plain;f=c%CE%BBash%2FCLasH%2FVHDL%2FGenerate.hs;h=431f3794dd01465f59937dbb16c65b58fdda051f;hb=88046cfef9b84647c507e215891896c79b66443e;hp=aea597679b85071769f50e40db2b0da8971df997;hpb=ad9bc80c39c42f645c76c65e1d3833148b854c1e;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git

diff --git "a/c\316\273ash/CLasH/VHDL/Generate.hs" "b/c\316\273ash/CLasH/VHDL/Generate.hs"
index aea5976..431f379 100644
--- "a/c\316\273ash/CLasH/VHDL/Generate.hs"
+++ "b/c\316\273ash/CLasH/VHDL/Generate.hs"
@@ -47,7 +47,7 @@ getEntity fname = Utils.makeCached fname tsEntities $ do
       -- Strip off lambda's, these will be arguments
       let (args, letexpr) = CoreSyn.collectBinders expr
       -- Generate ports for all non-state types
-      args' <- catMaybesM $ mapM mkMap (filter (not.hasStateType) args)
+      args' <- catMaybesM $ mapM mkMap args
       -- There must be a let at top level 
       let (CoreSyn.Let binds (CoreSyn.Var res)) = letexpr
       -- TODO: Handle Nothing