X-Git-Url: https://git.stderr.nl/gitweb?a=blobdiff_plain;f=c%CE%BBash%2FCLasH%2FVHDL%2FGenerate.hs;h=0b2cf04d6b2e171b459186607aa3530a203c7060;hb=374a42ba3cf333ae53fa1d992620d25286641ae2;hp=5698ef89a6efe29503b4c263b524c288a46f0016;hpb=643dc9319b6a2a3df54b258194c4534764fe1df2;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git

diff --git "a/c\316\273ash/CLasH/VHDL/Generate.hs" "b/c\316\273ash/CLasH/VHDL/Generate.hs"
index 5698ef8..0b2cf04 100644
--- "a/c\316\273ash/CLasH/VHDL/Generate.hs"
+++ "b/c\316\273ash/CLasH/VHDL/Generate.hs"
@@ -778,7 +778,7 @@ genApplication dst f args = do
           -- TODO: Using show here isn't really pretty, but we'll need some
           -- unique-ish value...
           let label = "comp_ins_" ++ (either show prettyShow) dst
-          let portmaps = mkAssocElems args' ((either varToVHDLName id) dst) signature
+          portmaps <- mkAssocElems args' ((either varToVHDLName id) dst) signature
           return ([mkComponentInst label entity_id portmaps], [f])
         False -> do
           -- Not a top level binder, so this must be a local variable reference.