X-Git-Url: https://git.stderr.nl/gitweb?a=blobdiff_plain;f=c%CE%BBash%2FCLasH%2FVHDL%2FConstants.hs;h=6051d9b3168e8cb132b3b66ed04fa33bc8676b78;hb=07a6394442d0d83a754af8f0d90f3702bb1821c6;hp=03688eb01a132eed54233a00088719dff82f2d13;hpb=4f5949f4e4451111010d1a4f67206f07b41f77a5;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git

diff --git "a/c\316\273ash/CLasH/VHDL/Constants.hs" "b/c\316\273ash/CLasH/VHDL/Constants.hs"
index 03688eb..6051d9b 100644
--- "a/c\316\273ash/CLasH/VHDL/Constants.hs"
+++ "b/c\316\273ash/CLasH/VHDL/Constants.hs"
@@ -1,7 +1,22 @@
 module CLasH.VHDL.Constants where
-  
+
+-- VHDL Imports  
 import qualified Language.VHDL.AST as AST
 
+-- | A list of all builtin functions. Partly duplicates the name table
+-- in VHDL.Generate, but we can't use that map everywhere due to
+-- circular dependencie.
+builtinIds = [ exId, replaceId, headId, lastId, tailId, initId, takeId, dropId
+             , selId, plusgtId, ltplusId, plusplusId, mapId, zipWithId, foldlId
+             , foldrId, zipId, unzipId, shiftlId, shiftrId, rotlId, rotrId
+             , concatId, reverseId, iteratenId, iterateId, generatenId, generateId
+             , emptyId, singletonId, copynId, copyId, lengthTId, nullId
+             , hwxorId, hwandId, hworId, hwnotId, equalityId, inEqualityId, ltId
+             , lteqId, gtId, gteqId, boolOrId, boolAndId, plusId, timesId
+             , negateId, minusId, fromSizedWordId, fromIntegerId, resizeWordId
+             , resizeIntId, sizedIntId, smallIntegerId, fstId, sndId, blockRAMId
+             , splitId, minimumId, fromRangedWordId 
+             ]
 --------------
 -- Identifiers
 --------------
@@ -235,6 +250,9 @@ fstId = "fst"
 sndId :: String
 sndId = "snd"
 
+splitId :: String
+splitId = "split"
+
 -- Equality Operations
 equalityId :: String
 equalityId = "=="
@@ -260,6 +278,9 @@ boolOrId = "||"
 boolAndId :: String
 boolAndId = "&&"
 
+boolNot :: String
+boolNot = "not"
+
 -- Numeric Operations
 
 -- | plus operation identifier
@@ -282,6 +303,9 @@ minusId = "-"
 fromSizedWordId :: String
 fromSizedWordId = "fromSizedWord"
 
+fromRangedWordId :: String
+fromRangedWordId = "fromRangedWord"
+
 toIntegerId :: String
 toIntegerId = "to_integer"
 
@@ -297,6 +321,12 @@ toUnsignedId = "to_unsigned"
 resizeId :: String
 resizeId = "resize"
 
+resizeWordId :: String
+resizeWordId = "resizeWord"
+
+resizeIntId :: String
+resizeIntId = "resizeInt"
+
 smallIntegerId :: String
 smallIntegerId = "smallInteger"
 
@@ -366,4 +396,4 @@ stringTM = AST.unsafeVHDLBasicId "string"
 
 -- | tup VHDLName suffix
 tupVHDLSuffix :: AST.VHDLId -> AST.Suffix
-tupVHDLSuffix id = AST.SSimple id
\ No newline at end of file
+tupVHDLSuffix id = AST.SSimple id