X-Git-Url: https://git.stderr.nl/gitweb?a=blobdiff_plain;f=c%CE%BBash%2FCLasH%2FVHDL%2FConstants.hs;h=22bf14aabaac4e047905c5b8d7cf916fc9cc6768;hb=f3951a1376fc7d7f8addbe9e9fed071320502100;hp=f465d848642c6e8b47e92716ea652af784992f03;hpb=4c63601269c7097e2177c547dc36d4edecc1c648;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git

diff --git "a/c\316\273ash/CLasH/VHDL/Constants.hs" "b/c\316\273ash/CLasH/VHDL/Constants.hs"
index f465d84..22bf14a 100644
--- "a/c\316\273ash/CLasH/VHDL/Constants.hs"
+++ "b/c\316\273ash/CLasH/VHDL/Constants.hs"
@@ -1,5 +1,6 @@
 module CLasH.VHDL.Constants where
-  
+
+-- VHDL Imports  
 import qualified Language.VHDL.AST as AST
 
 --------------
@@ -16,6 +17,8 @@ resetId, clockId :: AST.VHDLId
 resetId = AST.unsafeVHDLBasicId resetStr
 clockId = AST.unsafeVHDLBasicId clockStr
 
+integerId :: AST.VHDLId
+integerId = AST.unsafeVHDLBasicId "integer"
 
 -- | \"types\" identifier
 typesId :: AST.VHDLId
@@ -123,6 +126,9 @@ initId = "init"
 tailId :: String
 tailId = "tail"
 
+-- | minimum ftp function identifier
+minimumId :: String
+minimumId = "minimum"
 
 -- | take function identifier
 takeId :: String
@@ -224,6 +230,40 @@ hwandId = "hwand"
 lengthTId :: String
 lengthTId = "lengthT"
 
+fstId :: String
+fstId = "fst"
+
+sndId :: String
+sndId = "snd"
+
+splitId :: String
+splitId = "split"
+
+-- Equality Operations
+equalityId :: String
+equalityId = "=="
+
+inEqualityId :: String
+inEqualityId = "/="
+
+gtId :: String
+gtId = ">"
+
+ltId :: String
+ltId = "<"
+
+gteqId :: String
+gteqId = ">="
+
+lteqId :: String
+lteqId = "<="
+
+boolOrId :: String
+boolOrId = "||"
+
+boolAndId :: String
+boolAndId = "&&"
+
 -- Numeric Operations
 
 -- | plus operation identifier
@@ -261,12 +301,30 @@ toUnsignedId = "to_unsigned"
 resizeId :: String
 resizeId = "resize"
 
+resizeWordId :: String
+resizeWordId = "resizeWord"
+
+resizeIntId :: String
+resizeIntId = "resizeInt"
+
+smallIntegerId :: String
+smallIntegerId = "smallInteger"
+
+sizedIntId :: String
+sizedIntId = "SizedInt"
+
+tfvecId :: String
+tfvecId = "TFVec"
+
+blockRAMId :: String
+blockRAMId = "blockRAM"
+
 -- | output file identifier (from std.textio)
 showIdString :: String
 showIdString = "show"
 
 showId :: AST.VHDLId
-showId = AST.unsafeVHDLBasicId showIdString
+showId = AST.unsafeVHDLExtId showIdString
 
 -- | write function identifier (from std.textio)
 writeId :: AST.VHDLId
@@ -311,3 +369,11 @@ signedTM = AST.unsafeVHDLBasicId "signed"
 -- | unsigned TypeMark
 unsignedTM :: AST.TypeMark
 unsignedTM = AST.unsafeVHDLBasicId "unsigned"
+
+-- | string TypeMark
+stringTM :: AST.TypeMark
+stringTM = AST.unsafeVHDLBasicId "string"
+
+-- | tup VHDLName suffix
+tupVHDLSuffix :: AST.VHDLId -> AST.Suffix
+tupVHDLSuffix id = AST.SSimple id
\ No newline at end of file