X-Git-Url: https://git.stderr.nl/gitweb?a=blobdiff_plain;f=c%CE%BBash%2FCLasH%2FVHDL%2FConstants.hs;h=22bf14aabaac4e047905c5b8d7cf916fc9cc6768;hb=f3951a1376fc7d7f8addbe9e9fed071320502100;hp=b0236f5364351ec63b333aabc1940c34193d1259;hpb=d699d2f50e6d172308ef56adec01ace357ef0a0f;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git

diff --git "a/c\316\273ash/CLasH/VHDL/Constants.hs" "b/c\316\273ash/CLasH/VHDL/Constants.hs"
index b0236f5..22bf14a 100644
--- "a/c\316\273ash/CLasH/VHDL/Constants.hs"
+++ "b/c\316\273ash/CLasH/VHDL/Constants.hs"
@@ -1,5 +1,6 @@
 module CLasH.VHDL.Constants where
-  
+
+-- VHDL Imports  
 import qualified Language.VHDL.AST as AST
 
 --------------
@@ -229,9 +230,39 @@ hwandId = "hwand"
 lengthTId :: String
 lengthTId = "lengthT"
 
+fstId :: String
+fstId = "fst"
+
+sndId :: String
+sndId = "snd"
+
+splitId :: String
+splitId = "split"
+
 -- Equality Operations
-equalsId :: String
-equalsId = "=="
+equalityId :: String
+equalityId = "=="
+
+inEqualityId :: String
+inEqualityId = "/="
+
+gtId :: String
+gtId = ">"
+
+ltId :: String
+ltId = "<"
+
+gteqId :: String
+gteqId = ">="
+
+lteqId :: String
+lteqId = "<="
+
+boolOrId :: String
+boolOrId = "||"
+
+boolAndId :: String
+boolAndId = "&&"
 
 -- Numeric Operations
 
@@ -270,6 +301,12 @@ toUnsignedId = "to_unsigned"
 resizeId :: String
 resizeId = "resize"
 
+resizeWordId :: String
+resizeWordId = "resizeWord"
+
+resizeIntId :: String
+resizeIntId = "resizeInt"
+
 smallIntegerId :: String
 smallIntegerId = "smallInteger"
 
@@ -279,6 +316,9 @@ sizedIntId = "SizedInt"
 tfvecId :: String
 tfvecId = "TFVec"
 
+blockRAMId :: String
+blockRAMId = "blockRAM"
+
 -- | output file identifier (from std.textio)
 showIdString :: String
 showIdString = "show"