X-Git-Url: https://git.stderr.nl/gitweb?a=blobdiff_plain;f=c%CE%BBash%2FCLasH%2FTranslator%2FTranslatorTypes.hs;h=ee2220d0a4ece1ff6de9e2cfcd9ad193615a5b81;hb=60afa8f89d02ac5818d525d6209efe703cc22086;hp=47deeef9844d6089871ac3af4277c17513acae29;hpb=59a43e6286b2b5cebbdc427768efdcd28dc71dad;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git diff --git "a/c\316\273ash/CLasH/Translator/TranslatorTypes.hs" "b/c\316\273ash/CLasH/Translator/TranslatorTypes.hs" index 47deeef..ee2220d 100644 --- "a/c\316\273ash/CLasH/Translator/TranslatorTypes.hs" +++ "b/c\316\273ash/CLasH/Translator/TranslatorTypes.hs" @@ -27,7 +27,7 @@ import CLasH.VHDL.VHDLTypes -- | A specification of an entity we can generate VHDL for. Consists of the -- binder of the top level entity, an optional initial state and an optional -- test input. -type EntitySpec = (CoreSyn.CoreBndr, Maybe CoreSyn.CoreExpr, Maybe CoreSyn.CoreExpr) +type EntitySpec = (Maybe CoreSyn.CoreBndr, Maybe CoreSyn.CoreExpr, Maybe CoreSyn.CoreExpr) -- | A function that knows which parts of a module to compile type Finder = @@ -47,6 +47,7 @@ instance Ord OrdType where data HType = StdType OrdType | ADTType String [HType] | + EnumType String [String] | VecType Int HType | SizedWType Int | RangedWType Int | @@ -60,7 +61,7 @@ type TypeMap = Map.Map HType (Maybe (AST.VHDLId, Either AST.TypeDef AST.SubtypeI -- A map of a vector Core element type and function name to the coressponding -- VHDLId of the function and the function body. -type TypeFunMap = Map.Map (OrdType, String) (AST.VHDLId, AST.SubProgBody) +type TypeFunMap = Map.Map (HType, String) (AST.VHDLId, AST.SubProgBody) type TfpIntMap = Map.Map OrdType Int -- A substate that deals with type generation @@ -86,6 +87,7 @@ data TranslatorState = TranslatorState { , tsType_ :: TypeState , tsBindings_ :: Map.Map CoreSyn.CoreBndr CoreSyn.CoreExpr , tsNormalized_ :: Map.Map CoreSyn.CoreBndr CoreSyn.CoreExpr + , tsEntityCounter_ :: Integer , tsEntities_ :: Map.Map CoreSyn.CoreBndr Entity , tsArchitectures_ :: Map.Map CoreSyn.CoreBndr (Architecture, [CoreSyn.CoreBndr]) }