X-Git-Url: https://git.stderr.nl/gitweb?a=blobdiff_plain;f=c%CE%BBash%2FCLasH%2FTranslator%2FTranslatorTypes.hs;h=7483504fd08c12083c4ff58038eca4a916ffafe5;hb=cf53d927025a818188af17622903df33ade92ff8;hp=de7ee52055b23835174e29571c8172df04705283;hpb=b83ea5327202d46fc976e369ac303608cbc2330e;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git

diff --git "a/c\316\273ash/CLasH/Translator/TranslatorTypes.hs" "b/c\316\273ash/CLasH/Translator/TranslatorTypes.hs"
index de7ee52..7483504 100644
--- "a/c\316\273ash/CLasH/Translator/TranslatorTypes.hs"
+++ "b/c\316\273ash/CLasH/Translator/TranslatorTypes.hs"
@@ -12,6 +12,7 @@ import qualified Data.Accessor.Template
 import Data.Accessor
 
 -- GHC API
+import qualified GHC
 import qualified CoreSyn
 import qualified Type
 import qualified HscTypes
@@ -23,8 +24,22 @@ import qualified Language.VHDL.AST as AST
 -- Local imports
 import CLasH.VHDL.VHDLTypes
 
+-- | A specification of an entity we can generate VHDL for. Consists of the
+--   binder of the top level entity, an optional initial state and an optional
+--   test input.
+type EntitySpec = (Maybe CoreSyn.CoreBndr, Maybe CoreSyn.CoreExpr, Maybe CoreSyn.CoreExpr)
+
+-- | A function that knows which parts of a module to compile
+type Finder =
+  HscTypes.CoreModule -- ^ The module to look at
+  -> GHC.Ghc [EntitySpec]
+
+-----------------------------------------------------------------------------
+-- The TranslatorSession
+-----------------------------------------------------------------------------
+
 -- A orderable equivalent of CoreSyn's Type for use as a map key
-newtype OrdType = OrdType { getType :: Type.Type }
+newtype OrdType = OrdType Type.Type
 instance Eq OrdType where
   (OrdType a) == (OrdType b) = Type.tcEqType a b
 instance Ord OrdType where
@@ -39,8 +54,9 @@ data HType = StdType OrdType |
              BuiltinType String
   deriving (Eq, Ord)
 
--- A map of a Core type to the corresponding type name
-type TypeMap = Map.Map HType (AST.VHDLId, Either AST.TypeDef AST.SubtypeIn)
+-- A map of a Core type to the corresponding type name, or Nothing when the
+-- type would be empty.
+type TypeMap = Map.Map HType (Maybe (AST.VHDLId, Either AST.TypeDef AST.SubtypeIn))
 
 -- A map of a vector Core element type and function name to the coressponding
 -- VHDLId of the function and the function body.
@@ -70,6 +86,7 @@ data TranslatorState = TranslatorState {
   , tsType_ :: TypeState
   , tsBindings_ :: Map.Map CoreSyn.CoreBndr CoreSyn.CoreExpr
   , tsNormalized_ :: Map.Map CoreSyn.CoreBndr CoreSyn.CoreExpr
+  , tsEntityCounter_ :: Integer
   , tsEntities_ :: Map.Map CoreSyn.CoreBndr Entity
   , tsArchitectures_ :: Map.Map CoreSyn.CoreBndr (Architecture, [CoreSyn.CoreBndr])
 }