X-Git-Url: https://git.stderr.nl/gitweb?a=blobdiff_plain;f=c%CE%BBash%2FCLasH%2FTranslator%2FTranslatorTypes.hs;h=12ca6ed8ea9313f59ecd035e8d2e299a6d58bbc6;hb=a54863feb7304aa6a843efc15d29f017c45407f4;hp=7483504fd08c12083c4ff58038eca4a916ffafe5;hpb=aa2503aeb4cfa5540633db2cdd50bea20b5f1c50;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git diff --git "a/c\316\273ash/CLasH/Translator/TranslatorTypes.hs" "b/c\316\273ash/CLasH/Translator/TranslatorTypes.hs" index 7483504..12ca6ed 100644 --- "a/c\316\273ash/CLasH/Translator/TranslatorTypes.hs" +++ "b/c\316\273ash/CLasH/Translator/TranslatorTypes.hs" @@ -23,11 +23,12 @@ import qualified Language.VHDL.AST as AST -- Local imports import CLasH.VHDL.VHDLTypes +import CLasH.Translator.Annotations -- | A specification of an entity we can generate VHDL for. Consists of the -- binder of the top level entity, an optional initial state and an optional -- test input. -type EntitySpec = (Maybe CoreSyn.CoreBndr, Maybe CoreSyn.CoreExpr, Maybe CoreSyn.CoreExpr) +type EntitySpec = (Maybe CoreSyn.CoreBndr, Maybe [(CoreSyn.CoreBndr, CoreSyn.CoreBndr)], Maybe CoreSyn.CoreExpr) -- | A function that knows which parts of a module to compile type Finder = @@ -47,6 +48,7 @@ instance Ord OrdType where data HType = StdType OrdType | ADTType String [HType] | + EnumType String [String] | VecType Int HType | SizedWType Int | RangedWType Int | @@ -60,7 +62,7 @@ type TypeMap = Map.Map HType (Maybe (AST.VHDLId, Either AST.TypeDef AST.SubtypeI -- A map of a vector Core element type and function name to the coressponding -- VHDLId of the function and the function body. -type TypeFunMap = Map.Map (OrdType, String) (AST.VHDLId, AST.SubProgBody) +type TypeFunMap = Map.Map (HType, String) (AST.VHDLId, AST.SubProgBody) type TfpIntMap = Map.Map OrdType Int -- A substate that deals with type generation @@ -89,6 +91,7 @@ data TranslatorState = TranslatorState { , tsEntityCounter_ :: Integer , tsEntities_ :: Map.Map CoreSyn.CoreBndr Entity , tsArchitectures_ :: Map.Map CoreSyn.CoreBndr (Architecture, [CoreSyn.CoreBndr]) + , tsInitStates_ :: Map.Map CoreSyn.CoreBndr CoreSyn.CoreBndr } -- Derive accessors