X-Git-Url: https://git.stderr.nl/gitweb?a=blobdiff_plain;f=c%CE%BBash%2FCLasH%2FHardwareTypes.hs;h=c3eaf4396ef0eb2c65c991cfabdeef9eacd2a986;hb=51a7bd0bb429d112154578fdd1dfd706e6e01f6e;hp=9209086db466642dde74e6d4967f418b1ea5a3e9;hpb=08b9e0c5831fc9ea188395b6e272359bf439568f;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git

diff --git "a/c\316\273ash/CLasH/HardwareTypes.hs" "b/c\316\273ash/CLasH/HardwareTypes.hs"
index 9209086..c3eaf43 100644
--- "a/c\316\273ash/CLasH/HardwareTypes.hs"
+++ "b/c\316\273ash/CLasH/HardwareTypes.hs"
@@ -1,4 +1,4 @@
-{-# LANGUAGE TemplateHaskell, DeriveDataTypeable #-}
+{-# LANGUAGE TemplateHaskell, DeriveDataTypeable, FlexibleContexts, TypeFamilies, TypeOperators #-}
 
 module CLasH.HardwareTypes
   ( module Types
@@ -8,11 +8,15 @@ module CLasH.HardwareTypes
   , module Data.SizedWord
   , module Prelude
   , Bit(..)
+  , State(..)
   , Vector
   , hwand
   , hwor
   , hwxor
   , hwnot
+  , RAM
+  , MemState
+  , blockRAM
   ) where
 
 import qualified Prelude as P
@@ -29,6 +33,8 @@ import Data.SizedWord
 import Language.Haskell.TH.Lift
 import Data.Typeable
 
+newtype State s = State s deriving (P.Show)
+
 type Vector = TFVec.TFVec
 
 -- The plain Bit type
@@ -54,4 +60,27 @@ Low `hwxor` High = High
 _ `hwxor` _      = Low
 
 hwnot High = Low
-hwnot Low  = High
\ No newline at end of file
+hwnot Low  = High
+
+type RAM s a          = Vector (s :+: D1) a
+
+type MemState s a      = State (RAM s a)
+
+blockRAM :: 
+  (NaturalT s
+  ,PositiveT (s :+: D1)
+  ,((s :+: D1) :>: s) ~ True ) =>
+  (MemState s a) -> 
+  a ->
+  RangedWord s ->
+  RangedWord s ->
+  Bit -> 
+  ((MemState s a), a )
+blockRAM (State mem) data_in rdaddr wraddr wrenable = 
+  ((State mem'), data_out)
+  where
+    data_out  = mem!rdaddr
+    -- Only write data_in to memory if write is enabled
+    mem' = case wrenable of
+      Low   ->  mem
+      High  ->  replace mem wraddr data_in