X-Git-Url: https://git.stderr.nl/gitweb?a=blobdiff_plain;f=VHDLTypes.hs;h=f317167a86b857a02f675f8570c03b07cbe52805;hb=c5bde4d7862c7df2b4bad183088f77a43d8b5a2c;hp=a5d1569eb5728ebce6ec43223f5446674383bf9e;hpb=998e440a7fa765685e1ed500c871058a33129b1f;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git

diff --git a/VHDLTypes.hs b/VHDLTypes.hs
index a5d1569..f317167 100644
--- a/VHDLTypes.hs
+++ b/VHDLTypes.hs
@@ -44,6 +44,9 @@ instance Ord OrdType where
 -- A map of a Core type to the corresponding type name
 type TypeMap = Map.Map OrdType (AST.VHDLId, AST.TypeDec)
 
+-- A map of a vector Core type to the coressponding VHDL functions
+type TypeFunMap = Map.Map OrdType [AST.SubProgBody]
+
 -- A map of a Haskell function to a hardware signature
 type SignatureMap = Map.Map HsFunction Entity
 
@@ -52,10 +55,14 @@ type NameTable = Map.Map String (Int, [AST.Expr] -> AST.Expr )
 
 data VHDLSession = VHDLSession {
   -- | A map of Core type -> VHDL Type
-  vsTypes_ :: TypeMap,
+  vsTypes_      :: TypeMap,
+  -- | A map of vector Core type -> VHDL type function
+  vsTypeFuns_   :: TypeFunMap,
   -- | A map of HsFunction -> hardware signature (entity name, port names,
   --   etc.)
-  vsSignatures_ :: SignatureMap
+  vsSignatures_ :: SignatureMap,
+  -- | A map of Vector HsFunctions -> VHDL function call
+  vsNameTable_  :: NameTable
 }
 
 -- Derive accessors