X-Git-Url: https://git.stderr.nl/gitweb?a=blobdiff_plain;f=VHDLTypes.hs;h=b4c1d6981c2f757df4fb7c5049375aa4845bcb59;hb=969bf6e8931f58606a1d8bfe288539ded8369553;hp=ff159fa895a6f4c51318eaaf636c2d390e36e2f6;hpb=c8034ff49822eb6e0e0696f288e20e49a1b9af6e;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git

diff --git a/VHDLTypes.hs b/VHDLTypes.hs
index ff159fa..b4c1d69 100644
--- a/VHDLTypes.hs
+++ b/VHDLTypes.hs
@@ -13,6 +13,7 @@ import qualified Data.Accessor.Template
 -- GHC API imports
 import qualified Type
 import qualified CoreSyn
+import qualified HscTypes
 
 -- ForSyDe imports
 import qualified ForSyDe.Backend.VHDL.AST as AST
@@ -40,7 +41,10 @@ instance Ord OrdType where
 
 data HType = StdType OrdType |
              ADTType String [HType] |
-             VecType Int HType |
+             VecType OrdType HType |
+             SizedWType Int |
+             RangedWType Int |
+             SizedIType Int |
              BuiltinType String
   deriving (Eq, Ord)
 
@@ -54,18 +58,20 @@ type TypeFunMap = Map.Map (OrdType, String) (AST.VHDLId, AST.SubProgBody)
 -- A map of a Haskell function to a hardware signature
 type SignatureMap = Map.Map CoreSyn.CoreBndr Entity
 
+type TfpIntMap = Map.Map OrdType Int
+
 data TypeState = TypeState {
   -- | A map of Core type -> VHDL Type
   vsTypes_      :: TypeMap,
   -- | A list of type declarations
   vsTypeDecls_  :: [AST.PackageDecItem],
   -- | A map of vector Core type -> VHDL type function
-  vsTypeFuns_   :: TypeFunMap
+  vsTypeFuns_   :: TypeFunMap,
+  vsTfpInts_    :: TfpIntMap,
+  vsHscEnv_     :: HscTypes.HscEnv
 }
 -- Derive accessors
 $( Data.Accessor.Template.deriveAccessors ''TypeState )
--- Define an empty TypeState
-emptyTypeState = TypeState Map.empty [] Map.empty
 -- Define a session
 type TypeSession = State.State TypeState