X-Git-Url: https://git.stderr.nl/gitweb?a=blobdiff_plain;f=VHDLTypes.hs;h=b4c1d6981c2f757df4fb7c5049375aa4845bcb59;hb=46f93616d6a7ef012c5f07698d56372881196015;hp=e8a77377f87d4833963b817c6812a9e4b0699fd9;hpb=59b710f483534efd4a293f880235f444a5156451;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git

diff --git a/VHDLTypes.hs b/VHDLTypes.hs
index e8a7737..b4c1d69 100644
--- a/VHDLTypes.hs
+++ b/VHDLTypes.hs
@@ -13,6 +13,7 @@ import qualified Data.Accessor.Template
 -- GHC API imports
 import qualified Type
 import qualified CoreSyn
+import qualified HscTypes
 
 -- ForSyDe imports
 import qualified ForSyDe.Backend.VHDL.AST as AST
@@ -38,11 +39,17 @@ instance Eq OrdType where
 instance Ord OrdType where
   compare (OrdType a) (OrdType b) = Type.tcCmpType a b
 
--- A map of a Core type to the corresponding type name
-type TypeMap = Map.Map OrdType (AST.VHDLId, Either AST.TypeDef AST.SubtypeIn)
+data HType = StdType OrdType |
+             ADTType String [HType] |
+             VecType OrdType HType |
+             SizedWType Int |
+             RangedWType Int |
+             SizedIType Int |
+             BuiltinType String
+  deriving (Eq, Ord)
 
--- A map of Elem types to the corresponding VHDL Id for the Vector
-type ElemTypeMap = Map.Map OrdType (AST.VHDLId, AST.TypeDef)
+-- A map of a Core type to the corresponding type name
+type TypeMap = Map.Map HType (AST.VHDLId, Either AST.TypeDef AST.SubtypeIn)
 
 -- A map of a vector Core element type and function name to the coressponding
 -- VHDLId of the function and the function body.
@@ -51,13 +58,26 @@ type TypeFunMap = Map.Map (OrdType, String) (AST.VHDLId, AST.SubProgBody)
 -- A map of a Haskell function to a hardware signature
 type SignatureMap = Map.Map CoreSyn.CoreBndr Entity
 
-data VHDLState = VHDLState {
+type TfpIntMap = Map.Map OrdType Int
+
+data TypeState = TypeState {
   -- | A map of Core type -> VHDL Type
   vsTypes_      :: TypeMap,
-  -- | A map of Elem types -> VHDL Vector Id
-  vsElemTypes_   :: ElemTypeMap,
+  -- | A list of type declarations
+  vsTypeDecls_  :: [AST.PackageDecItem],
   -- | A map of vector Core type -> VHDL type function
   vsTypeFuns_   :: TypeFunMap,
+  vsTfpInts_    :: TfpIntMap,
+  vsHscEnv_     :: HscTypes.HscEnv
+}
+-- Derive accessors
+$( Data.Accessor.Template.deriveAccessors ''TypeState )
+-- Define a session
+type TypeSession = State.State TypeState
+
+data VHDLState = VHDLState {
+  -- | A subtype with typing info
+  vsType_       :: TypeState,
   -- | A map of HsFunction -> hardware signature (entity name, port names,
   --   etc.)
   vsSignatures_ :: SignatureMap
@@ -69,9 +89,6 @@ $( Data.Accessor.Template.deriveAccessors ''VHDLState )
 -- | The state containing a VHDL Session
 type VHDLSession = State.State VHDLState
 
--- | A substate containing just the types
-type TypeState = State.State TypeMap
-
 -- A function that generates VHDL for a builtin function
 type BuiltinBuilder = 
   (Either CoreSyn.CoreBndr AST.VHDLName) -- ^ The destination signal and it's original type