X-Git-Url: https://git.stderr.nl/gitweb?a=blobdiff_plain;f=VHDLTypes.hs;h=b3eaa9201f9c7bfc1b2147caba773395ee31cbc7;hb=597f1b6823417f2c4cc54549f2a9d1b9f131893c;hp=5b6807bdbc5a1864db4e636f9626007322982b44;hpb=e03f02c419b4365d498c25dfbc861215394046df;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git

diff --git a/VHDLTypes.hs b/VHDLTypes.hs
index 5b6807b..b3eaa92 100644
--- a/VHDLTypes.hs
+++ b/VHDLTypes.hs
@@ -43,20 +43,27 @@ instance Ord OrdType where
   compare (OrdType a) (OrdType b) = Type.tcCmpType a b
 
 -- A map of a Core type to the corresponding type name
-type TypeMap = Map.Map OrdType (AST.VHDLId, AST.TypeDef)
+type TypeMap = Map.Map OrdType (AST.VHDLId, Either AST.TypeDef AST.SubtypeIn)
+
+-- A map of Elem types to the corresponding VHDL Id for the Vector
+type ElemTypeMap = Map.Map OrdType (AST.VHDLId, AST.TypeDef)
 
 -- A map of a vector Core type to the coressponding VHDL functions
 type TypeFunMap = Map.Map OrdType [AST.SubProgBody]
 
 -- A map of a Haskell function to a hardware signature
-type SignatureMap = Map.Map String Entity
+type SignatureMap = Map.Map CoreSyn.CoreBndr Entity
+
+type Builder = Either ([AST.Expr] -> AST.Expr) (Entity -> [CoreSyn.CoreBndr] -> AST.GenerateSm)
 
 -- A map of a builtin function to VHDL function builder 
-type NameTable = Map.Map String (Int, [AST.Expr] -> AST.Expr )
+type NameTable = Map.Map String (Int, Builder )
 
 data VHDLSession = VHDLSession {
   -- | A map of Core type -> VHDL Type
   vsTypes_      :: TypeMap,
+  -- | A map of Elem types -> VHDL Vector Id
+  vsElemTypes_   :: ElemTypeMap,
   -- | A map of vector Core type -> VHDL type function
   vsTypeFuns_   :: TypeFunMap,
   -- | A map of HsFunction -> hardware signature (entity name, port names,