X-Git-Url: https://git.stderr.nl/gitweb?a=blobdiff_plain;f=VHDLTypes.hs;h=9fdfbf1b0c34ef35679675680c1902f8c2e5db42;hb=0de275199ba2f3a98339eefb7784e061a451c5f7;hp=9ae197c4e99ea9bfa80bb858227396c3522cd810;hpb=b2a68b424663d5a909791080c416a54088321936;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git

diff --git a/VHDLTypes.hs b/VHDLTypes.hs
index 9ae197c..9fdfbf1 100644
--- a/VHDLTypes.hs
+++ b/VHDLTypes.hs
@@ -6,8 +6,11 @@ module VHDLTypes where
 import qualified ForSyDe.Backend.VHDL.AST as AST
 
 import FlattenTypes
+import HsValueMap
 
-type VHDLSignalMap = SignalMap (AST.VHDLId, AST.TypeMark)
+-- | A mapping from a haskell structure to the corresponding VHDL port
+--   signature, or Nothing for values that do not translate to a port.
+type VHDLSignalMap = HsValueMap (Maybe (AST.VHDLId, AST.TypeMark))
 
 -- A description of a VHDL entity. Contains both the entity itself as well as
 -- info on how to map a haskell value (argument / result) on to the entity's
@@ -16,5 +19,6 @@ data Entity = Entity {
   ent_id     :: AST.VHDLId,           -- The id of the entity
   ent_args   :: [VHDLSignalMap],      -- A mapping of each function argument to port names
   ent_res    :: VHDLSignalMap,        -- A mapping of the function result to port names
-  ent_decl   :: Maybe AST.EntityDec   -- The actual entity declaration. Can be empty for builtin functions.
+  ent_decl   :: Maybe AST.EntityDec,  -- The actual entity declaration. Can be empty for builtin functions.
+  ent_pkg_decl :: Maybe AST.PackageDec -- A package declaration with types for this entity
 }