X-Git-Url: https://git.stderr.nl/gitweb?a=blobdiff_plain;f=VHDLTypes.hs;h=95e9ce02d9d239fa888e0727a0d3aa77ee1dd77a;hb=d21c34b00b9041a146da89324e9dda6b22271b47;hp=9b48579600e86e4977f871a79f4898a82a3f27f4;hpb=91914df9b344ccf0bc3242dc28ce74a8d6721944;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git

diff --git a/VHDLTypes.hs b/VHDLTypes.hs
index 9b48579..95e9ce0 100644
--- a/VHDLTypes.hs
+++ b/VHDLTypes.hs
@@ -43,10 +43,10 @@ instance Ord OrdType where
   compare (OrdType a) (OrdType b) = Type.tcCmpType a b
 
 -- A map of a Core type to the corresponding type name
-type TypeMap = Map.Map OrdType (AST.VHDLId, AST.TypeDec)
+type TypeMap = Map.Map OrdType (AST.VHDLId, Either AST.TypeDef AST.SubtypeIn)
 
--- A map of a Core type to the corresponding VHDL subtype
-type SubTypeMap = Map.Map OrdType (AST.VHDLId, AST.SubtypeDec)
+-- A map of Elem types to the corresponding VHDL Id for the Vector
+type ElemTypeMap = Map.Map OrdType (AST.VHDLId, AST.TypeDef)
 
 -- A map of a vector Core type to the coressponding VHDL functions
 type TypeFunMap = Map.Map OrdType [AST.SubProgBody]
@@ -60,8 +60,8 @@ type NameTable = Map.Map String (Int, [AST.Expr] -> AST.Expr )
 data VHDLSession = VHDLSession {
   -- | A map of Core type -> VHDL Type
   vsTypes_      :: TypeMap,
-  -- | A map of Core type -> VHDL SubType
-  vsSubTypes_   :: SubTypeMap,
+  -- | A map of Elem types -> VHDL Vector Id
+  vsElemTypes_   :: ElemTypeMap,
   -- | A map of vector Core type -> VHDL type function
   vsTypeFuns_   :: TypeFunMap,
   -- | A map of HsFunction -> hardware signature (entity name, port names,