X-Git-Url: https://git.stderr.nl/gitweb?a=blobdiff_plain;f=VHDLTypes.hs;h=87120436510620829be57115f5f52ff15933114c;hb=b8c1e8554ba8aee73bc9d9a54bb3cb32f7930957;hp=b4c1d6981c2f757df4fb7c5049375aa4845bcb59;hpb=758998d6ef18ab5124c65518781c358d76d229ab;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git

diff --git a/VHDLTypes.hs b/VHDLTypes.hs
index b4c1d69..8712043 100644
--- a/VHDLTypes.hs
+++ b/VHDLTypes.hs
@@ -16,7 +16,7 @@ import qualified CoreSyn
 import qualified HscTypes
 
 -- ForSyDe imports
-import qualified ForSyDe.Backend.VHDL.AST as AST
+import qualified Language.VHDL.AST as AST
 
 -- Local imports
 
@@ -41,7 +41,7 @@ instance Ord OrdType where
 
 data HType = StdType OrdType |
              ADTType String [HType] |
-             VecType OrdType HType |
+             VecType Int HType |
              SizedWType Int |
              RangedWType Int |
              SizedIType Int |