X-Git-Url: https://git.stderr.nl/gitweb?a=blobdiff_plain;f=VHDLTypes.hs;h=784b09706e6a6742a4fb504640983e8973349225;hb=3f12ee5d723fd8c01190c5971641141a8c7a9d98;hp=33010822b9ace9ec74e0002e0ba015fd2643254b;hpb=b9aa3bd5f003fe7604d0610629c3771245b9ef90;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git

diff --git a/VHDLTypes.hs b/VHDLTypes.hs
index 3301082..784b097 100644
--- a/VHDLTypes.hs
+++ b/VHDLTypes.hs
@@ -12,6 +12,7 @@ import qualified Data.Accessor.Template
 
 -- GHC API imports
 import qualified Type
+import qualified CoreSyn
 
 -- ForSyDe imports
 import qualified ForSyDe.Backend.VHDL.AST as AST
@@ -30,8 +31,8 @@ type VHDLSignalMap = HsValueMap VHDLSignalMapElement
 -- ports.
 data Entity = Entity { 
   ent_id     :: AST.VHDLId,           -- The id of the entity
-  ent_args   :: [VHDLSignalMap],      -- A mapping of each function argument to port names
-  ent_res    :: VHDLSignalMap         -- A mapping of the function result to port names
+  ent_args   :: [VHDLSignalMapElement],      -- A mapping of each function argument to port names
+  ent_res    :: VHDLSignalMapElement         -- A mapping of the function result to port names
 } deriving (Show);
 
 -- A orderable equivalent of CoreSyn's Type for use as a map key
@@ -45,7 +46,7 @@ instance Ord OrdType where
 type TypeMap = Map.Map OrdType (AST.VHDLId, AST.TypeDec)
 
 -- A map of a Haskell function to a hardware signature
-type SignatureMap = Map.Map HsFunction Entity
+type SignatureMap = Map.Map String Entity
 
 data VHDLSession = VHDLSession {
   -- | A map of Core type -> VHDL Type