X-Git-Url: https://git.stderr.nl/gitweb?a=blobdiff_plain;f=VHDLTypes.hs;h=74084864dc8c3c9f8d8a1aa27a433e4a7cf8132a;hb=193c179bc6abf610796b6076aee9f9b557d4b106;hp=44696479e6719de98c5f3f67bdcd6aa261b7e808;hpb=a8d7c5bd4b745860f321d4315bff0b9efa3cb05c;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git

diff --git a/VHDLTypes.hs b/VHDLTypes.hs
index 4469647..7408486 100644
--- a/VHDLTypes.hs
+++ b/VHDLTypes.hs
@@ -6,14 +6,19 @@ module VHDLTypes where
 import qualified ForSyDe.Backend.VHDL.AST as AST
 
 import FlattenTypes
+import HsValueMap
 
-type VHDLSignalMap = SignalMap (AST.VHDLId, AST.TypeMark)
+-- | A mapping from a haskell structure to the corresponding VHDL port
+--   signature, or Nothing for values that do not translate to a port.
+type VHDLSignalMap = HsValueMap (Maybe (AST.VHDLId, AST.TypeMark))
 
 -- A description of a VHDL entity. Contains both the entity itself as well as
 -- info on how to map a haskell value (argument / result) on to the entity's
 -- ports.
 data Entity = Entity {
+  ent_id     :: AST.VHDLId,           -- The id of the entity
   ent_args   :: [VHDLSignalMap],      -- A mapping of each function argument to port names
   ent_res    :: VHDLSignalMap,        -- A mapping of the function result to port names
-  ent_decl   :: Maybe AST.EntityDec   -- The actual entity declaration. Can be empty for builtin functions.
-}
+  ent_decl   :: Maybe AST.EntityDec,  -- The actual entity declaration. Can be empty for builtin functions.
+  ent_pkg_decl :: Maybe AST.PackageDec -- A package declaration with types for this entity
+} deriving (Show);