X-Git-Url: https://git.stderr.nl/gitweb?a=blobdiff_plain;f=VHDLTypes.hs;h=61fb0035650002fa61c95db39bb6c56429114bfb;hb=f5f6d286f56ee1e822ece0258039ba2d2ce920aa;hp=3a8bce12f88e4fef661449443dd72a4d0c05e20a;hpb=4d96e10ba2805470597642cf4c2ba797eda1b1f9;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git

diff --git a/VHDLTypes.hs b/VHDLTypes.hs
index 3a8bce1..61fb003 100644
--- a/VHDLTypes.hs
+++ b/VHDLTypes.hs
@@ -18,21 +18,17 @@ import qualified CoreSyn
 import qualified ForSyDe.Backend.VHDL.AST as AST
 
 -- Local imports
-import FlattenTypes
-import HsValueMap
 
-type VHDLSignalMapElement = (Maybe (AST.VHDLId, AST.TypeMark))
--- | A mapping from a haskell structure to the corresponding VHDL port
---   signature, or Nothing for values that do not translate to a port.
-type VHDLSignalMap = HsValueMap VHDLSignalMapElement
+-- A description of a port of an entity
+type Port = (AST.VHDLId, AST.TypeMark)
 
 -- A description of a VHDL entity. Contains both the entity itself as well as
 -- info on how to map a haskell value (argument / result) on to the entity's
 -- ports.
 data Entity = Entity { 
   ent_id     :: AST.VHDLId,           -- The id of the entity
-  ent_args   :: [VHDLSignalMapElement],      -- A mapping of each function argument to port names
-  ent_res    :: VHDLSignalMapElement         -- A mapping of the function result to port names
+  ent_args   :: [Port],      -- A mapping of each function argument to port names
+  ent_res    :: Port         -- A mapping of the function result to port names
 } deriving (Show);
 
 -- A orderable equivalent of CoreSyn's Type for use as a map key
@@ -45,11 +41,9 @@ instance Ord OrdType where
 -- A map of a Core type to the corresponding type name
 type TypeMap = Map.Map OrdType (AST.VHDLId, Either AST.TypeDef AST.SubtypeIn)
 
--- A map of Elem types to the corresponding VHDL Id for the Vector
-type ElemTypeMap = Map.Map OrdType (AST.VHDLId, AST.TypeDef)
-
--- A map of a vector Core type to the coressponding VHDL functions
-type TypeFunMap = Map.Map OrdType [AST.SubProgBody]
+-- A map of a vector Core element type and function name to the coressponding
+-- VHDLId of the function and the function body.
+type TypeFunMap = Map.Map (OrdType, String) (AST.VHDLId, AST.SubProgBody)
 
 -- A map of a Haskell function to a hardware signature
 type SignatureMap = Map.Map CoreSyn.CoreBndr Entity
@@ -57,8 +51,8 @@ type SignatureMap = Map.Map CoreSyn.CoreBndr Entity
 data VHDLState = VHDLState {
   -- | A map of Core type -> VHDL Type
   vsTypes_      :: TypeMap,
-  -- | A map of Elem types -> VHDL Vector Id
-  vsElemTypes_   :: ElemTypeMap,
+  -- | A list of type declarations
+  vsTypeDecls_  :: [AST.PackageDecItem],
   -- | A map of vector Core type -> VHDL type function
   vsTypeFuns_   :: TypeFunMap,
   -- | A map of HsFunction -> hardware signature (entity name, port names,
@@ -75,9 +69,15 @@ type VHDLSession = State.State VHDLState
 -- | A substate containing just the types
 type TypeState = State.State TypeMap
 
-type Builder = Either ([AST.Expr] -> VHDLSession AST.Expr) (Entity -> [CoreSyn.CoreBndr] -> VHDLSession AST.GenerateSm)
+-- A function that generates VHDL for a builtin function
+type BuiltinBuilder = 
+  (Either CoreSyn.CoreBndr AST.VHDLName) -- ^ The destination signal and it's original type
+  -> CoreSyn.CoreBndr -- ^ The function called
+  -> [Either CoreSyn.CoreExpr AST.Expr] -- ^ The value arguments passed (excluding type and
+                    --   dictionary arguments).
+  -> VHDLSession [AST.ConcSm] -- ^ The resulting concurrent statements.
 
 -- A map of a builtin function to VHDL function builder 
-type NameTable = Map.Map String (Int, Builder )
+type NameTable = Map.Map String (Int, BuiltinBuilder )
 
 -- vim: set ts=8 sw=2 sts=2 expandtab: