X-Git-Url: https://git.stderr.nl/gitweb?a=blobdiff_plain;f=VHDLTypes.hs;h=59da9c17341dfc1d63f70f89673159071848055a;hb=12fc969daa4ca2dfc69ab68f27684dd6b01622f3;hp=a5d1569eb5728ebce6ec43223f5446674383bf9e;hpb=998e440a7fa765685e1ed500c871058a33129b1f;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git

diff --git a/VHDLTypes.hs b/VHDLTypes.hs
index a5d1569..59da9c1 100644
--- a/VHDLTypes.hs
+++ b/VHDLTypes.hs
@@ -12,6 +12,7 @@ import qualified Data.Accessor.Template
 
 -- GHC API imports
 import qualified Type
+import qualified CoreSyn
 
 -- ForSyDe imports
 import qualified ForSyDe.Backend.VHDL.AST as AST
@@ -30,8 +31,8 @@ type VHDLSignalMap = HsValueMap VHDLSignalMapElement
 -- ports.
 data Entity = Entity { 
   ent_id     :: AST.VHDLId,           -- The id of the entity
-  ent_args   :: [VHDLSignalMap],      -- A mapping of each function argument to port names
-  ent_res    :: VHDLSignalMap         -- A mapping of the function result to port names
+  ent_args   :: [VHDLSignalMapElement],      -- A mapping of each function argument to port names
+  ent_res    :: VHDLSignalMapElement         -- A mapping of the function result to port names
 } deriving (Show);
 
 -- A orderable equivalent of CoreSyn's Type for use as a map key
@@ -42,29 +43,41 @@ instance Ord OrdType where
   compare (OrdType a) (OrdType b) = Type.tcCmpType a b
 
 -- A map of a Core type to the corresponding type name
-type TypeMap = Map.Map OrdType (AST.VHDLId, AST.TypeDec)
+type TypeMap = Map.Map OrdType (AST.VHDLId, Either AST.TypeDef AST.SubtypeIn)
 
--- A map of a Haskell function to a hardware signature
-type SignatureMap = Map.Map HsFunction Entity
+-- A map of Elem types to the corresponding VHDL Id for the Vector
+type ElemTypeMap = Map.Map OrdType (AST.VHDLId, AST.TypeDef)
 
--- A map of a builtin function to VHDL function builder 
-type NameTable = Map.Map String (Int, [AST.Expr] -> AST.Expr )
+-- A map of a vector Core type to the coressponding VHDL functions
+type TypeFunMap = Map.Map OrdType [AST.SubProgBody]
+
+-- A map of a Haskell function to a hardware signature
+type SignatureMap = Map.Map CoreSyn.CoreBndr Entity
 
-data VHDLSession = VHDLSession {
+data VHDLState = VHDLState {
   -- | A map of Core type -> VHDL Type
-  vsTypes_ :: TypeMap,
+  vsTypes_      :: TypeMap,
+  -- | A map of Elem types -> VHDL Vector Id
+  vsElemTypes_   :: ElemTypeMap,
+  -- | A map of vector Core type -> VHDL type function
+  vsTypeFuns_   :: TypeFunMap,
   -- | A map of HsFunction -> hardware signature (entity name, port names,
   --   etc.)
   vsSignatures_ :: SignatureMap
 }
 
 -- Derive accessors
-$( Data.Accessor.Template.deriveAccessors ''VHDLSession )
+$( Data.Accessor.Template.deriveAccessors ''VHDLState )
 
 -- | The state containing a VHDL Session
-type VHDLState = State.State VHDLSession
+type VHDLSession = State.State VHDLState
 
 -- | A substate containing just the types
 type TypeState = State.State TypeMap
 
+type Builder = Either ([AST.Expr] -> AST.Expr) (Entity -> [CoreSyn.CoreBndr] -> AST.GenerateSm)
+
+-- A map of a builtin function to VHDL function builder 
+type NameTable = Map.Map String (Int, Builder )
+
 -- vim: set ts=8 sw=2 sts=2 expandtab: