X-Git-Url: https://git.stderr.nl/gitweb?a=blobdiff_plain;f=VHDLTypes.hs;h=59da9c17341dfc1d63f70f89673159071848055a;hb=12fc969daa4ca2dfc69ab68f27684dd6b01622f3;hp=95e9ce02d9d239fa888e0727a0d3aa77ee1dd77a;hpb=98734f52c51081459172bd28c0913162264cf3e5;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git

diff --git a/VHDLTypes.hs b/VHDLTypes.hs
index 95e9ce0..59da9c1 100644
--- a/VHDLTypes.hs
+++ b/VHDLTypes.hs
@@ -52,12 +52,9 @@ type ElemTypeMap = Map.Map OrdType (AST.VHDLId, AST.TypeDef)
 type TypeFunMap = Map.Map OrdType [AST.SubProgBody]
 
 -- A map of a Haskell function to a hardware signature
-type SignatureMap = Map.Map String Entity
+type SignatureMap = Map.Map CoreSyn.CoreBndr Entity
 
--- A map of a builtin function to VHDL function builder 
-type NameTable = Map.Map String (Int, [AST.Expr] -> AST.Expr )
-
-data VHDLSession = VHDLSession {
+data VHDLState = VHDLState {
   -- | A map of Core type -> VHDL Type
   vsTypes_      :: TypeMap,
   -- | A map of Elem types -> VHDL Vector Id
@@ -66,18 +63,21 @@ data VHDLSession = VHDLSession {
   vsTypeFuns_   :: TypeFunMap,
   -- | A map of HsFunction -> hardware signature (entity name, port names,
   --   etc.)
-  vsSignatures_ :: SignatureMap,
-  -- | A map of Vector HsFunctions -> VHDL function call
-  vsNameTable_  :: NameTable
+  vsSignatures_ :: SignatureMap
 }
 
 -- Derive accessors
-$( Data.Accessor.Template.deriveAccessors ''VHDLSession )
+$( Data.Accessor.Template.deriveAccessors ''VHDLState )
 
 -- | The state containing a VHDL Session
-type VHDLState = State.State VHDLSession
+type VHDLSession = State.State VHDLState
 
 -- | A substate containing just the types
 type TypeState = State.State TypeMap
 
+type Builder = Either ([AST.Expr] -> AST.Expr) (Entity -> [CoreSyn.CoreBndr] -> AST.GenerateSm)
+
+-- A map of a builtin function to VHDL function builder 
+type NameTable = Map.Map String (Int, Builder )
+
 -- vim: set ts=8 sw=2 sts=2 expandtab: