X-Git-Url: https://git.stderr.nl/gitweb?a=blobdiff_plain;f=VHDLTypes.hs;h=3a8bce12f88e4fef661449443dd72a4d0c05e20a;hb=6fffdcf32a54a6372442d22a87537ee9733073ad;hp=fe739da7149545bd4bc3d58f7a04c239ae89cf57;hpb=6e874e80511177529f7d4506d78f69002ba69e68;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git

diff --git a/VHDLTypes.hs b/VHDLTypes.hs
index fe739da..3a8bce1 100644
--- a/VHDLTypes.hs
+++ b/VHDLTypes.hs
@@ -54,11 +54,6 @@ type TypeFunMap = Map.Map OrdType [AST.SubProgBody]
 -- A map of a Haskell function to a hardware signature
 type SignatureMap = Map.Map CoreSyn.CoreBndr Entity
 
-type Builder = Either ([AST.Expr] -> AST.Expr) (Entity -> [CoreSyn.CoreBndr] -> AST.GenerateSm)
-
--- A map of a builtin function to VHDL function builder 
-type NameTable = Map.Map String (Int, Builder )
-
 data VHDLState = VHDLState {
   -- | A map of Core type -> VHDL Type
   vsTypes_      :: TypeMap,
@@ -68,9 +63,7 @@ data VHDLState = VHDLState {
   vsTypeFuns_   :: TypeFunMap,
   -- | A map of HsFunction -> hardware signature (entity name, port names,
   --   etc.)
-  vsSignatures_ :: SignatureMap,
-  -- | A map of Vector HsFunctions -> VHDL function call
-  vsNameTable_  :: NameTable
+  vsSignatures_ :: SignatureMap
 }
 
 -- Derive accessors
@@ -82,4 +75,9 @@ type VHDLSession = State.State VHDLState
 -- | A substate containing just the types
 type TypeState = State.State TypeMap
 
+type Builder = Either ([AST.Expr] -> VHDLSession AST.Expr) (Entity -> [CoreSyn.CoreBndr] -> VHDLSession AST.GenerateSm)
+
+-- A map of a builtin function to VHDL function builder 
+type NameTable = Map.Map String (Int, Builder )
+
 -- vim: set ts=8 sw=2 sts=2 expandtab: