X-Git-Url: https://git.stderr.nl/gitweb?a=blobdiff_plain;f=VHDLTypes.hs;h=26ed823d904f35dd6653513f84cf2788e81ddac2;hb=e273d2759db01787f0599a1cbe9059864e1704d7;hp=1704bb874dc453a4475fe1657eb622e638ccb02c;hpb=7bb29e6c00a94229f48663afb6e128d24b3ad7f9;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git

diff --git a/VHDLTypes.hs b/VHDLTypes.hs
index 1704bb8..26ed823 100644
--- a/VHDLTypes.hs
+++ b/VHDLTypes.hs
@@ -6,10 +6,11 @@ module VHDLTypes where
 import qualified ForSyDe.Backend.VHDL.AST as AST
 
 import FlattenTypes
+import HsValueMap
 
 -- | A mapping from a haskell structure to the corresponding VHDL port
 --   signature, or Nothing for values that do not translate to a port.
-type VHDLSignalMap = SignalMap (Maybe (AST.VHDLId, AST.TypeMark))
+type VHDLSignalMap = HsValueMap (Maybe (AST.VHDLId, AST.TypeMark))
 
 -- A description of a VHDL entity. Contains both the entity itself as well as
 -- info on how to map a haskell value (argument / result) on to the entity's