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diff --git a/VHDLTypes.hs b/VHDLTypes.hs
index 9ae197c..26ed823 100644
--- a/VHDLTypes.hs
+++ b/VHDLTypes.hs
@@ -6,8 +6,11 @@ module VHDLTypes where
 import qualified ForSyDe.Backend.VHDL.AST as AST
 
 import FlattenTypes
+import HsValueMap
 
-type VHDLSignalMap = SignalMap (AST.VHDLId, AST.TypeMark)
+-- | A mapping from a haskell structure to the corresponding VHDL port
+--   signature, or Nothing for values that do not translate to a port.
+type VHDLSignalMap = HsValueMap (Maybe (AST.VHDLId, AST.TypeMark))
 
 -- A description of a VHDL entity. Contains both the entity itself as well as
 -- info on how to map a haskell value (argument / result) on to the entity's