X-Git-Url: https://git.stderr.nl/gitweb?a=blobdiff_plain;f=VHDLTypes.hs;h=1704bb874dc453a4475fe1657eb622e638ccb02c;hb=7bb29e6c00a94229f48663afb6e128d24b3ad7f9;hp=9ae197c4e99ea9bfa80bb858227396c3522cd810;hpb=b2a68b424663d5a909791080c416a54088321936;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git

diff --git a/VHDLTypes.hs b/VHDLTypes.hs
index 9ae197c..1704bb8 100644
--- a/VHDLTypes.hs
+++ b/VHDLTypes.hs
@@ -7,7 +7,9 @@ import qualified ForSyDe.Backend.VHDL.AST as AST
 
 import FlattenTypes
 
-type VHDLSignalMap = SignalMap (AST.VHDLId, AST.TypeMark)
+-- | A mapping from a haskell structure to the corresponding VHDL port
+--   signature, or Nothing for values that do not translate to a port.
+type VHDLSignalMap = SignalMap (Maybe (AST.VHDLId, AST.TypeMark))
 
 -- A description of a VHDL entity. Contains both the entity itself as well as
 -- info on how to map a haskell value (argument / result) on to the entity's