X-Git-Url: https://git.stderr.nl/gitweb?a=blobdiff_plain;f=VHDLTypes.hs;fp=VHDLTypes.hs;h=a533bf5989c0367ac5c62bf473299287df163127;hb=1643800a4ef64501806747d2cafe917be7b1b3b2;hp=d23daea033d77b38710b5fe6c09fcbfaae2be62f;hpb=02534f209c10759b7f1c8d3eedff5c742570de76;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git

diff --git a/VHDLTypes.hs b/VHDLTypes.hs
index d23daea..a533bf5 100644
--- a/VHDLTypes.hs
+++ b/VHDLTypes.hs
@@ -76,7 +76,7 @@ type VHDLSession = State.State VHDLState
 -- | A substate containing just the types
 type TypeState = State.State TypeMap
 
-type Builder = Either (CoreSyn.CoreBndr -> [AST.Expr] -> VHDLSession AST.Expr) (Entity -> [CoreSyn.CoreBndr] -> VHDLSession AST.GenerateSm)
+type Builder = Either (CoreSyn.CoreBndr -> [AST.Expr] -> VHDLSession AST.Expr) (Entity -> [CoreSyn.CoreBndr] -> VHDLSession AST.ConcSm)
 
 -- A map of a builtin function to VHDL function builder 
 type NameTable = Map.Map String (Int, Builder )